IP Library Granted Patent US 9,331,046
Granted Patent B2
US 9,331,046 · App. 14/315,766 · Granted May 3, 2016

Integrated circuit package with voltage distributor

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,331,046
App. No.
14/315,766
Granted
May 3, 2016
Kind
B2
Abstract

An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.

Claims (43)

1. A method of forming an integrated circuit package, comprising:

attaching a semiconductor die to a package support;

attaching a conductive distributor with an adhesive structure to the semiconductor die;

wire bonding a first plurality of bond pads on a periphery of the semiconductor die and a second plurality of bond pads on an interior portion of the semiconductor die to the conductive distributor;

wherein the conductive distributor includes one or more openings, the second plurality of bond pads are located in the one or more openings;

encapsulating the semiconductor die, the conductive distributor, and at least a portion of a top surface of the package support.

2. The method of claim 1 , wherein the attaching the conductive distributor includes carrying the distributor to the die with a vacuum suction tool.

3. The method of claim 1 wherein the conductive distributor is within a perimeter of the semiconductor die when attached to the semiconductor die.

4. The method of claim 3 wherein the first plurality of bond pads are located between the perimeter of the semiconductor die and a perimeter of the conductive distributor when the conductive distributor is attached to the semiconductor die.

5. The method of claim 1 wherein the conductive distributor includes a conductive layer, at least a first subset of bond pads of the second plurality of bond pads are wire bonded to the conductive layer.

6. The method of claim 1 wherein a first bond pad of the second plurality of bond pads is for a first power supply voltage domain of the semiconductor die, wherein a second bond pad of the second plurality of bond pads is for a second power supply voltage domain of the semiconductor die.

7. The method of claim 1 wherein the package support includes a plurality of wire bonding surfaces, the method further including wire bonding a bond pad of the semiconductor die to a wire bonding surface of the plurality of wire bonding surfaces.

8. The method of claim 7 wherein no bond wires of the integrated circuit package are connected to both a wire bonding surface of the package support and the conductive distributor.

9. The method of claim 7 wherein the bond pad of the semiconductor die is a bond pad of the first plurality of bond pads.

10. The method of claim 1 wherein the conductive distributor includes an outer portion, a center portion, and a plurality of arms connecting the outer portion to the center portion, wherein an opening of the one or more openings is defined by the outer portion, the center portion and two arms of the plurality of arms.

11. The method of claim 1 wherein:

the conductive distributor has a first conductive layer, a second conductive layer over the first conductive layer, and an insulator separating the first conductive layer and the second conductive layer;

the wire bonding the second plurality of bond pads on an interior portion of the semiconductor die to the conductive distributor includes wire bonding a first bond pad of the second plurality to the first conductive layer and wire bonding a second bond pad of the second plurality to the second conductive layer.

12. The method of claim 11 wherein, the wire bonding the first plurality of bond pads on a periphery of the semiconductor die to the conductive distributor includes wire bonding a third bond pad of the first plurality to the first conductor layer and wire bonding a fourth bond pad of the first plurality to the second conductive layer.

13. The method of claim 11 wherein the first bond pad is for a first power supply voltage domain and the second bond pad is for a second power supply voltage domain.

14. The method of claim 11 wherein the conductive distributor includes a first opening and the second opening, the first bond pad is in the first opening and the second bond pad is in the second opening.

15. The method of claim 11 wherein:

the conductive distributor includes a first opening and the second opening, the first pad is in the first opening and the second pad is in the first opening;

the second plurality of bond pads includes a third bond pad in the second opening and a fourth bond pad in the second opening;

wherein the wire bonding the second plurality of bond pads on an interior portion of the semiconductor die to the conductive distributor includes wire bonding the third bond pad to the first conductive layer and wire bonding the fourth bond pad to the second conductive layer.

16. A method of forming an integrated circuit package, comprising:

attaching a semiconductor die to a package support;

attaching a conductive distributor with an adhesive structure to the semiconductor die;

wire bonding a first plurality of bond pads on a periphery of the semiconductor die and a second plurality of bond pads on an interior portion of the semiconductor die to the conductive distributor;

encapsulating the semiconductor die, the conductive distributor, and at least a portion of a top surface of the package support;

wherein the conductive distributor is an interleaved distributor and includes a first conductive structure of a first power supply voltage domain of the semiconductor die and a second conductive structure of a second power supply voltage domain of the semiconductor die;

wherein a first bond pad of the first plurality and a second bond pad of the second plurality are coupled to the first conductive structure;

wherein a third bond wire of the first plurality and a fourth bond wire of the second plurality are coupled to the second conductive structure.

17. A method of forming an integrated circuit package, comprising:

attaching a semiconductor die to a package support;

attaching a conductive distributor with an adhesive structure to the semiconductor die;

wire bonding a first plurality of bond pads on a periphery of the semiconductor die and a second plurality of bond pads on an interior portion of the semiconductor die to the conductive distributor;

encapsulating the semiconductor die, the conductive distributor, and at least a portion of a top surface of the package support;

wherein the conductive distributor has a first conductive layer, a second conductive layer over the first conductive layer, and an insulator separating the first conductive layer and the second conductive layer;

wherein the wire bonding the second plurality of bond pads on an interior portion of the semiconductor die to the conductive distributor includes wire bonding a first bond pad of the second plurality to the first conductive layer and wire bonding a second bond pad of the second plurality to the second conductive layer.

18. The method of claim 17 wherein no bond wires of the integrated circuit package are connected to both a wire bonding surface of the package support and the conductive distributor.

19. The method of claim 17 wherein, the wire bonding the first plurality of bond pads on a periphery of the semiconductor die to the conductive distributor includes wire bonding a third bond pad of the first plurality to the first conductive layer and wire bonding a fourth bond pad of the first plurality to the second conductive layer.

20. The method of claim 17 wherein the first bond pad is for a first power supply voltage domain and the second bond pad is for a second power supply voltage domain.

Assignments (25)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0293 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0267 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033460/0337 →