Systems and methods for data conversion
View Patent ↗Systems and methods for electronically converting an analog signal to a digital signal are disclosed. The systems and methods may include, for a first bit value, setting a first conversion value to include a first offset; using the output of a first comparison, setting a second conversion value; and if the first bit value has a predetermined relationship to the first offset bit value, removing the first offset from the second conversion value, and, using the output of a second comparison, setting a third conversion value.
1. A system for converting an analog signal to a digital signal, the system comprising:
a redundancy element operable to provide an offset range;
a comparator coupled to a digital-to-analog converter (DAC), the comparator operable to compare a reference to an output associated with the DAC;
a control circuit coupled to the redundancy element, the control circuit operable to, for a first bit value:
communicate a first conversion value to the DAC, the first conversion value including a first offset, the first offset associated with a first offset bit value;
in response to a first comparison result from the comparator, setting a second conversion value; and
if the first bit value has a predetermined relationship to the first offset bit value, remove the first offset from the second conversion value; and
in response to a second comparison result from the comparator, setting a third conversion value.
2. The system of claim 1 , wherein the control circuit is further operable to transition to a second bit value in response to the second comparison result.
3. The system of claim 2 , wherein the control circuit is further operable to, for the second bit value:
communicate a fourth conversion value to a digital-to-analog converter (DAC), the fourth conversion value including a first offset, the first offset associated with a first offset bit value;
in response to a third comparison result from the comparator, setting a fifth conversion value; and
if the first bit value has a predetermined relationship to the first offset bit value, remove the first offset from the fifth conversion value; and
in response to a fourth comparison result from the comparator, setting a sixth conversion value.
4. The system of claim 3 , wherein the control circuit is further operable to set a seventh conversion value in response to the second comparison result, the seventh conversion value including a second offset, and the second offset associated with a second offset bit value.
5. The system of claim 4 , wherein the second offset is less than the first offset.
6. The system of claim 1 , wherein the DAC is a single-ended DAC.
7. The system of claim 1 , wherein the DAC is a differential DAC.
8. The system of claim 7 , wherein each of the conversion values comprises a pair of related conversion values.
9. The system of claim 1 , wherein the control circuit operates at a fixed clock rate.
10. The system of claim 1 , wherein the redundancy element is selected from the group consisting of: a capacitor, a voltage source, a current source, a selectable comparator offset, and an offset control circuit.
11. The system of claim 1 , wherein the redundancy element is part of the DAC.
12. The system of claim 1 , wherein the redundancy element is part of the comparator.
13. The system of claim 1 , further comprising a register coupled to the control circuit, the register operable to temporarily store the conversion values for access by the DAC.
14. The system of claim 7 , wherein the reference is an output of the differential DAC.
15. The system of claim 1 , wherein the predetermined relationship comprises the first bit value being one greater than the first offset bit value.
16. A method for electronically converting an analog signal to a digital signal, the method comprising:
for a first bit value, setting a first conversion value to include a first offset, the first offset associated with a first offset bit value;
using the output of a first comparison, setting a second conversion value; and
if the first bit value has a predetermined relationship to the first offset bit value, removing the first offset from the second conversion value; and
using the output of a second comparison, setting a third conversion value,
wherein setting the first conversion value comprises charging a bottom plate of a capacitor associated with the first bit value.
17. The method of claim 16 , further comprising after using the output of the second comparison, transitioning to a second bit value and repeating the steps of the method for the second bit value.
18. The method of claim 16 , further comprising, prior to using the output of the second comparison, setting a fourth conversion value to include a second offset, the second offset associated with a second offset bit value.
19. The method of claim 18 , wherein the second offset is less than the first offset.