IP Library Granted Patent US 9,851,941
Granted Patent B2
US 9,851,941 · App. 14/307,864 · Granted Dec 26, 2017

Method and apparatus for handling incoming data frames

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Quick Facts
Patent No.
US 9,851,941
App. No.
14/307,864
Granted
Dec 26, 2017
Kind
B2
Abstract

A method and apparatus for handling incoming data frames within a network interface controller. The network interface controller comprises at least one controller component operably coupled to at least one memory element. The at least one controller component is arranged to identify a next available buffer pointer from a pool of buffer pointers stored within a first area of memory within the at least one memory element, receive an indication that a start of a data frame has been received via a network interface, and allocate the identified next available buffer pointer to the data frame.

Claims (36)

1. A network interface controller comprising at least one controller component operably coupled to at least one memory element; the at least one controller component arranged to:

identify a next available buffer pointer from a pool of buffer pointers based at least partly on availability check bits for buffer pointer entries within the pool of buffer pointers, wherein the pool of buffer pointers are stored within a first area of memory within the at least one memory element;

load the identified next available buffer pointer into a buffer pointer register, wherein the buffer pointer register is a separate memory location the first area of memory that the pool of buffer pointers are stored;

receive a start of a data frame via a network interface after the identified next available buffer pointer is loaded into the buffer pointer register; and

allocate the identified next available buffer pointer to the data frame.

2. The network interface controller of claim 1 , wherein the at least one controller component is arranged to:

search buffer pointer entries within the pool of buffer pointers stored within the first area of memory for a buffer pointer entry comprising an availability check bit indicating the corresponding buffer pointer as being available; and

identify as the next available buffer pointer a buffer pointer from a buffer pointer entry comprising an availability check bit indicating the corresponding buffer pointer as being available.

3. The network interface controller of claim 2 , wherein the at least one controller component is arranged to update the availability check bit for the buffer pointer entry of the identified next available buffer pointer to indicate the corresponding buffer pointer as being unavailable, upon allocation of the identified next available buffer pointer to the data frame.

4. The network interface controller of claim 1 , wherein the at least one controller component is arranged to identify a subsequent next available buffer pointer from the pool of buffer pointers upon allocation of the present identified next available buffer pointer to the data frame.

5. The network interface controller of claim 1 , wherein the buffer pointer register is arranged to further have stored therein an indication of a size of the pool of buffer pointers.

6. The network interface controller of claim 5 , wherein the buffer pointer register is arranged to further have stored therein an indication of a location of the pool of buffer pointers within the first area of memory.

7. The network interface controller of claim 1 , wherein the at least one controller component is further arranged to:

generate a frame descriptor for the data frame being received, the frame descriptor comprising at least the identified next available buffer pointer allocated to the data frame; and

enqueue the frame descriptor within a frame descriptor queue within a second area of memory of the at least one memory element.

8. The network interface controller of claim 1 , wherein the network interface comprises at least one queue selection component arranged to select a frame descriptor queue within which to enqueue the frame descriptor for the data frame being received from a plurality of frame descriptor queues.

9. The network interface controller of claim 8 , wherein the at least one queue selection component is arranged to compare a pattern for the data frame being received to a pattern for each of at least a sub-set of the plurality of frame descriptor queues, and to select a frame descriptor queue within which to enqueue the frame descriptor for the data frame being received based at least partly on said comparison.

10. The network interface controller of claim 9 , wherein the network interface controller comprises a descriptor queue register corresponding to each of at least the sub-set of the plurality of frame descriptor queues, each descriptor queue register having stored therein at least the pattern for the respective frame descriptor queue.

11. The network interface controller of claim 10 , wherein each descriptor queue register further has stored therein a descriptor queue pointer for the respective frame descriptor queue, and the at least one controller component is arranged to enqueue the frame descriptor within the selected frame descriptor queue in accordance with the descriptor queue pointer stored within the descriptor queue register corresponding to the selected frame descriptor queue.

12. The network interface controller of claim 11 , wherein the at least one controller component is arranged to update the descriptor queue pointer stored within the descriptor queue register corresponding to the selected frame descriptor queue upon the frame descriptor for the data frame being enqueued therein.

13. The network interface controller of claim 12 , wherein each descriptor queue register is arranged to further have stored therein an indication of a size of the frame descriptor queue.

14. The network interface controller of claim 13 , wherein each descriptor queue register is arranged to further have stored therein an indication of a location of the frame descriptor queue within the second area of memory.

15. The network interface controller of claim 7 , wherein the at least one controller component is arranged to generate the frame descriptor for the data frame being received, the frame descriptor further comprising at least one of:

a timestamp value corresponding to the receipt of the start of the data frame being received;

a byte count for the data frame being received;

a flag indicating this is the last frame descriptor linked to a received frame; and

a cyclic redundancy check result for the data frame being received.

16. The network interface controller of claim 1 implemented within an integrated circuit device comprising at least one die within a single integrated circuit package.

17. A signal processing system comprising a network interface controller, the network interface controller comprising at least one controller component operably coupled to at least one memory element; the at least one controller component arranged to:

identify a next available buffer pointer from a pool of buffer pointers based at least partly on availability check bits for buffer pointer entries within the pool of buffer pointers, wherein the pool of buffer pointers are stored within a first area of memory within the at least one memory element, wherein the pool of buffer pointers is a single pool of buffer pointers associated with a plurality of frame descriptor queues;

receive a start of a data frame via a network interface; and

allocate the identified next available buffer pointer to the data frame.

18. A method of handling incoming data frames within a network interface controller, the method comprising, within a controller component of the network interface controller:

identifying a next available buffer pointer from a pool of buffer pointers based at least partly on availability check bits for buffer pointer entries within the pool of buffer pointers, wherein the pool of buffer pointers are stored within a first area of memory within at least one memory element operably coupled to the network interface controller, wherein the pool of buffer pointers is a single pool of buffer pointers associated with a plurality of frame descriptor queues;

receiving a start of a data frame via a network interface; and

allocating the identified next available buffer pointer to the data frame.

Assignments (18)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2021
From: NXP B.V.
To: FUTURE LINK SYSTEMS, LLC
Reel/Frame 055115/0491 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPLICATION 14/258,829 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0109. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0208 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 14/258,829 AND REPLACE ITWITH 14/258,629 PREVIOUSLY RECORDED ON REEL 037444 FRAME 0082. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OFSECURITY INTEREST IN PATENTS. Recorded Aug 10, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039639/0332 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0082 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0109 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0903 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0293 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033462/0267 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Aug 1, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 033460/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2014
From: RALSTON, JOHN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 033128/0247 →