Electrostatic discharge protection system
View Patent ↗An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.
1. An integrated circuit, comprising:
a first power bus;
a second power bus;
a core region;
a plurality of I/O cells around the core region, each I/O cell including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portion of the first power bus and the portion of the second power bus, wherein:
a first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit,
a second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge, wherein the first set is between the core region and the second set, and
for each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set;
an ESD clamp coupled between the first and second power buses; and
a trigger circuit coupled to the ESD clamp.
2. The integrated circuit of claim 1 , wherein the ESD clamp is part of a distributed clamp network having a plurality of clamps coupled between the first and second power buses.
3. The integrated circuit of claim 2 , wherein the trigger circuit is configured to, in response to an ESD event on any one of the I/O pads of the plurality of I/O cells, enable at least a portion of the plurality of clamps of the distributed clamp network.
4. The integrated circuit of claim 2 , wherein the distributed clamp network is located between the second set of I/O cells and the die edge.
5. The integrated circuit of claim 4 , wherein for each I/O cell in the second set, the portion of the first power bus is physically connected to the distributed ESD clamp network at a boundary between the I/O cell and the distributed ESD clamp network.
6. The integrated circuit of claim 1 , wherein:
for each I/O cell in the first set, the portion of the second power bus is physically connected to the portion of the second power bus of an abutting I/O cell of the second set at the boundary between the I/O cell of the first set and the abutting I/O cell of the second set.
7. The integrated circuit of claim 6 , wherein in each I/O cell of the plurality of I/O cells, the portion of the first bus is on a different metal level than the portion of the second bus.
8. The integrated circuit of claim 1 , wherein the first bus is further characterized as one of a VDDE bus or a VSSE bus, and the second bus is further characterized as another one of the VDDE bus or the VSSE bus.
9. The integrated circuit of claim 1 , wherein:
for each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the first set at a boundary between the I/O cell of the first set and the abutting I/O cell of the first set.
10. The integrated circuit of claim 1 , wherein:
for each I/O cell in the first set, the portion of the first power bus is also physically connected to the portion of the first power bus of a second abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the second abutting I/O cell of the second set.
11. An integrated circuit, comprising:
a first power bus;
a second power bus;
a plurality of I/O cells, each I/O cell including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portion of the first power bus and the portion of the second power bus, wherein the plurality of I/O cells is arranged into a first set of I/O cells having at least two I/O cells and a non-overlapping second set of I/O cells having at least two I/O cells; and
a distributed ESD clamp network including a second portion of the first power bus and a second portion of the second power bus, wherein:
the distributed ESD clamp network is located between the first set of I/O cells and the second set of I/O cells and abuts each I/O cell of the first set of I/O cells and each I/O cell of the second set of I/O cells, and
for each I/O cell in the first and second sets of I/O cells, the portion of the first power bus is physically connected to the second portion of the first power bus of the distributed ESD clamp network at a boundary between the I/O cell and the distributed ESD clamp network.
12. The integrated circuit of claim 11 , wherein:
for each I/O cell in the plurality of I/O cells, the portion of the second power bus is physically connected to the second portion of the second power bus of the distributed ESD clamp network at the boundary between the I/O cell and the distributed ESD clamp network.
13. The integrated circuit of claim 12 , wherein in each I/O cell of the plurality of I/O cells, the portion of the first bus is on a different metal level than the portion of the second bus.
14. The integrated circuit of claim 11 , wherein the distributed ESD clamp network comprises a plurality of clamps coupled between the second portion of the first power bus and the second portion of the second power bus.
15. The integrated circuit of claim 14 , further comprising a trigger circuit, wherein the trigger circuit is configured to, in response to an ESD event on any one of the I/O pads of the plurality of I/O cells, enable at least a portion of the plurality of clamps of the distributed clamp network.
16. The integrated circuit of claim 11 , wherein the first bus is further characterized as one of a VDDE bus or a VSSE bus, and the second bus is further characterized as another one of the VDDE bus or the VSSE bus.
17. An integrated circuit, comprising:
a VDDE bus;
a VSSE bus;
a core region;
a plurality of I/O cells around the core region, each I/O cell including a portion of the VDDE bus, a portion of the VSSE bus, and an I/O pad coupled between the portion of the VDDE bus and the portion of the VSSE bus, wherein:
a first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit,
a second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge, wherein the first set is between the core region and the second set and
for each I/O cell in the first set:
the portion of the VDDE bus is physically connected to the portion of the VDDE bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set, and
the portion of the VSSE bus is physically connected to the portion of the VSSE bus of the abutting I/O cell of the second set at the boundary between the I/O cell of the first set and the abutting I/O cell of the second set; and
an ESD clamp coupled between the VDDE bus and the VSSE bus; and
a trigger circuit coupled to the ESD clamp.
18. The integrated circuit of claim 17 , wherein the ESD clamp is part of a distributed clamp network having a plurality of clamps coupled between the VDDE bus and the VSSE bus, wherein the trigger circuit is configured to, in response to an ESD event on any one of the I/O pads of the plurality of I/O cells, enable at least a portion of the plurality of clamps of the distributed clamp network.
19. The integrated circuit of claim 18 , wherein for each I/O cell in the second set:
the portion of the VDDE bus is physically connected to the distributed ESD clamp network at a boundary between the I/O cell and the distributed ESD clamp network, and
the portion of the VSSE bus is physically connected to the distributed ESD clamp network at the boundary between the I/O cell and the distributed ESD clamp network.
20. The integrated circuit of claim 17 , wherein, for each I/O cell in the first set:
the portion of the VDDE bus is also physically connected to the portion of the VDDE bus of a second abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the second abutting I/O cell of the second set, and
the portion of the VSSE bus is also physically connected to the portion of the VSSE bus of the second abutting I/O cell of the second set at the boundary between the I/O cell of the first set and the second abutting I/O cell of the second set.