Microelectronic packages having embedded sidewall substrates and methods for the producing thereof
View Patent ↗Methods for fabricating microelectronic packages and microelectronic packages are provided. In one embodiment, the microelectronic package fabrication method includes producing a molded panel containing a sidewall substrate. The molded panel is singulated to produce a Fan-Out Wafer Level Package core including a molded body having a fan-out region in which the sidewall substrate is embedded. A side connect trace is printed or otherwise formed on a sidewall of the Fan-Out Wafer Level Package core and extends at least partially across the embedded sidewall substrate.
1. A method for producing a microelectronic package, the method comprising:
embedding a sidewall substrate in a molded panel;
singulating the molded panel to produce a first Fan-Out Wafer Level Package (FO-WLP) core having a sidewall at which the embedded sidewall substrate is exposed; and
forming a side connect trace on the sidewall of the first FO-WLP core and extending at least partially across the embedded sidewall substrate.
2. The method of claim 1 wherein singulating comprises removing material from the embedded sidewall substrate to provide the embedded sidewall substrate with a singulated surface, and wherein forming comprises forming the side connect trace in contact with the singulated surface of the sidewall substrate.
3. The method of claim 2 wherein singulating comprises sawing the molded panel along one or more saw lanes extending through the embedded sidewall substrate.
4. The method of claim 1 further comprising producing the embedded sidewall substrate to include a substrate body composed of a material selected from a group consisting of a resin, a ceramic, silicon, gallium nitride, and gallium arsenide.
5. The method of claim 1 wherein the embedded sidewall substrate comprises a sidewall pad exposed at the sidewall after singulation of the molded panel, and wherein the side connect trace is formed in contact with the sidewall pad.
6. The method of claim 5 further comprising forming one or more Redistribution Layers (RDLs) over the molded panel prior to singulation thereof, the RDLs containing an interconnect line electrically coupled to the sidewall pad.
7. The method of claim 6 wherein sidewall pad has a surface area exposed through the sidewall, and wherein the surface area of the sidewall pad is greater than a cross-sectional area of the interconnect line, as taken along a cut plane orthogonal to an upper principal surface of the RDLs.
8. The method of claim 6 further comprising bonding a second FO-WLP core to the first FO-WLP core such that the first FO-WLP core and the second FO-WLP core are disposed in a stacked relationship, the first FO-WLP core and the second FO-WLP core electrically interconnected through the side connect trace.
9. The method of claim 1 further comprising singulating a wafer to produce the sidewall substrate along with a plurality of other sidewall substrates; and
wherein embedding comprises overmolding the sidewall substrate and the plurality of other sidewall substrates to produce the molded panel.
10. The method of claim 9 further comprising forming at least one metal level over the wafer prior to singulation thereof such that a singulated piece of the wafer defines a body of the sidewall substrate, while a singulated portion of the metal level defines an embedded sidewall pad overlying the body of the sidewall substrate.
11. A method for producing a microelectronic package, the method comprising:
producing a first Fan-Out Wafer Level Package (FO-WLP) core including a first molded body, a sidewall substrate embedded in a fan-out region of the first molded body, and a first sidewall pad exposed through a sidewall of the first molded body;
stacking the first FO-WLP core with a second FO-WLP core having a second molded body and a second sidewall pad exposed through the sidewall of the second molded body; and
forming a side connect trace extending from the first sidewall pad, over the sidewall substrate, and to the second sidewall pad to interconnect the first and second FO-WLP cores.
12. The method of claim 11 wherein the first and second FO-WLP cores are stacked while in panel form to yield a panel stack;
wherein the method further comprises singulating the panel stack to define the respective sidewalls of the first and second molded bodies; and
wherein singulating comprises sawing the panel stack along saw lanes, wherein at least one of the saw lanes extends through the sidewall substrate.
13. The method of claim 11 wherein the first molded body of the FO-WLP core is produced to have a fan-out region in which the sidewall substrate is embedded.
14. The method of claim 11 wherein the first FO-WLP core is produced to include a dielectric layer between the first sidewall pad and a substrate body of the embedded sidewall substrate.
15. The method of claim 14 further comprising selecting the first sidewall pad to be at least partially composed of a metal plated over the dielectric layer.
16. The method of claim 11 further comprising selecting the embedded sidewall substrate to have a substrate body composed at least partially of a resin, a ceramic, silicon, gallium nitride, or gallium arsenide.
17. The method of claim 11 further comprising selecting the embedded sidewall substrate to have a substrate body comprised of a singulated piece of a bulk silicon wafer.