Driver amplifier systems and methods of their operation
View Patent ↗The embodiments described herein provide a radio frequency (RF) driver amplifier and method of operation. In general, the driver amplifier facilitates high performance operation in RF devices while being implemented with only n-type transistors. Using only n-type transistors in the driver amplifier can increase the operating bandwidth of the driver amplifier. Furthermore, using only n-type transistors in the driver amplifier can simplify device fabrication. The driver amplifiers and methods described herein can be used in a variety of applications. As one specific example the driver amplifier can be used in a switch-mode power amplifier (SMPA). Such a SMPA can be configured to amplify a time varying signal, such as an RF.
1. A radio frequency (RF) driver amplifier comprising:
an input node coupled to an RF signal;
an output node;
a first transistor pair, the first transistor pair comprising a first transistor in series with a second transistor, the first transistor comprising an n-type transistor having a first gate, first source and first drain, the second transistor comprising an n-type transistor having a second gate, second source and second drain and wherein the output node is coupled to the first source and the second drain, and wherein the input node is coupled to the second gate;
a second transistor pair, the second transistor pair comprising a third transistor in series with a fourth transistor, the third transistor comprising an n-type transistor having a third gate, third source and third drain, the fourth transistor comprising an n-type transistor having a fourth gate, fourth source and fourth drain, and wherein the input node is coupled to the third gate and the fourth gate, and wherein the first gate is coupled to the third source; and
wherein the first transistor, the second transistor, the third transistor, and the fourth transistor all comprise enhancement mode devices.
2. The driver amplifier of claim 1 , wherein the second source and the fourth source are each coupled to a voltage source and a first capacitor, with the first capacitor coupled to a first ground to provide AC ground through the first capacitor, and wherein the voltage source provides a negative DC bias with respect to the first ground.
3. The driver amplifier of claim 2 , wherein the output node is coupled to an output transistor, and wherein the output transistor has a negative threshold voltage with respect to the first ground.
4. The driver amplifier of claim 1 , wherein the driver amplifier is configured in a branch of a switch-mode power amplifier (SMPA) that includes a plurality of branches.
5. A radio frequency (RF) driver amplifier comprising:
an input node coupled to an RF signal;
an output node;
a first transistor pair, the first transistor pair comprising a first transistor in series with a second transistor, the first transistor comprising an n-type transistor having a first gate, first source and first drain, the second transistor comprising an n-type transistor having a second gate, second source and second drain and wherein the output node is coupled to the first source and the second drain, and wherein the input node is coupled to the second gate;
a second transistor pair, the second transistor pair comprising a third transistor in series with a fourth transistor, the third transistor comprising an n-type transistor having a third gate, third source and third drain, the fourth transistor comprising an n-type transistor having a fourth gate, fourth source and fourth drain, and wherein the input node is coupled to the third gate and the fourth gate, and wherein the first gate is coupled to the third source;
a fifth transistor comprising an n-type transistor having a fifth gate, fifth source and fifth drain; and
a sixth transistor comprising an n-type transistor having a sixth gate, sixth source and sixth drain, and wherein:
the input node is coupled to the second gate by coupling the sixth gate to the input node and coupling the sixth drain to the second gate;
the input node is coupled to the third gate by coupling sixth drain to the fifth gate and coupling the fifth drain to the third gate; and
the input node is coupled to the fourth gate by coupling sixth drain to the fourth gate.
6. The driver amplifier of claim 5 , wherein the first transistor, the second transistor, the third transistor, and the fourth transistor all comprise enhancement mode devices.
7. A radio frequency (RF) driver amplifier comprising:
an input node coupled to an RF signal;
an output node;
a first transistor pair, the first transistor pair comprising a first transistor in series with a second transistor, the first transistor comprising an n-type transistor having a first gate, first source and first drain, the second transistor comprising an n-type transistor having a second gate, second source and second drain and wherein the output node is coupled to the first source and the second drain, and wherein the input node is coupled to the second gate;
a second transistor pair, the second transistor pair comprising a third transistor in series with a fourth transistor, the third transistor comprising an n-type transistor having a third gate, third source and third drain, the fourth transistor comprising an n-type transistor having a fourth gate, fourth source and fourth drain, and wherein the input node is coupled to the third gate and the fourth gate, and wherein the first gate is coupled to the third source;
a fifth transistor comprising an n-type transistor having a fifth gate, fifth source and fifth drain;
a sixth transistor comprising an n-type transistor having a sixth gate, sixth source and sixth drain;
a seventh transistor comprising an n-type transistor having a seventh gate, seventh source and seventh drain; and
an eighth transistor comprising an n-type transistor having a eighth gate, eighth source and eighth drain, and wherein
the input node is coupled to the second gate by coupling the sixth gate to the input node, coupling the sixth drain to the seventh gate, the seventh drain to the eighth gate, and the eighth drain to the second gate;
the input node is coupled to the third gate by coupling sixth drain to the fifth gate and coupling the fifth drain to the third gate; and
the input node is coupled to the fourth gate by coupling eighth drain to the fourth gate.
8. The driver amplifier of claim 7 , wherein second source, the fourth source, the fifth source and the sixth source, the seventh source, and the eighth source are each coupled to a voltage source and a first capacitor, with the first capacitor coupled to a first ground to provide AC ground through the first capacitor, and wherein the voltage source provides a negative DC bias with respect to the first ground.
9. An amplifier comprising:
a number, N, of switch-mode power amplifier (SMPA) branches, wherein N is greater than one, and wherein each SMPA branch includes:
two drive signal inputs, so that the amplifier has a total of 2*N drive signal inputs,
one SMPA branch output, so that the amplifier has a total of N SMPA branch outputs, and
two driver amplifiers, each driver amplifier coupled to one of the two drive signal inputs, and wherein each of the two driver amplifiers includes:
a first transistor pair, the first transistor pair comprising a first transistor in series with a second transistor, the first transistor comprising an n-type transistor having a first gate, first source and first drain, the second transistor comprising an n-type transistor having a second gate, second source and second drain and wherein the corresponding SMPA branch output is coupled to the first source and the second drain, and wherein one of the corresponding drive signal inputs is coupled to the second gate; and
a second transistor pair, the second transistor pair comprising a third transistor in series with a fourth transistor, the third transistor comprising an n-type transistor having a third gate, third source and third drain, the fourth transistor comprising an n-type transistor having a fourth gate, fourth source and fourth drain, and wherein the one of the corresponding drive signal inputs is coupled to the third gate and the fourth gate, and wherein the first gate is coupled to the third source, and wherein,
in response to receiving a first combination of drive signals at the two drive signal inputs, each SMPA branch is configured to produce, at the SMPA branch output, an SMPA branch output signal at a first voltage level, and
in response to receiving a different second combination of drive signals at the two drive signal inputs, each SMPA branch is configured to produce, at the SMPA branch output, the SMPA branch output signal at a different second voltage level.
10. The amplifier of claim 9 , wherein each of the two driver amplifiers further comprises:
a fifth transistor comprising an n-type transistor having a fifth gate, fifth source and fifth drain;
a sixth transistor comprising an n-type transistor having a sixth gate, sixth source and sixth drain, and wherein:
the drive signal input is coupled to the second gate by coupling the sixth gate to the drive signal input and coupling the sixth drain to the second gate;
the drive signal input is coupled to the third gate by coupling sixth drain to the fifth gate and coupling the fifth drain to the third gate; and
the drive signal input is coupled to the fourth gate by coupling sixth drain to the fourth gate.
11. The amplifier of claim 9 , wherein for each of the two driver amplifiers the second source and the fourth source are each coupled to a voltage source and a first capacitor, with the first capacitor coupled to a first ground to provide AC ground through the first capacitor, and wherein the voltage source provides a negative DC bias with respect to the first ground.
12. The amplifier of claim 11 , wherein for each of the two driver amplifiers the SMPA branch output is coupled to a corresponding output transistor, and wherein each corresponding output transistor has a negative threshold voltage with respect to the first ground.
13. The amplifier of claim 9 , wherein each of the two driver amplifiers further comprises:
a fifth transistor comprising an n-type transistor having a fifth gate, fifth source and fifth drain;
a sixth transistor comprising an n-type transistor having a sixth gate, sixth source and sixth drain,
a seventh transistor comprising an n-type transistor having a seventh gate, seventh source and seventh drain,
an eighth transistor comprising an n-type transistor having a eighth gate, eighth source and eighth drain, and wherein
the drive signal input is coupled to the second gate by coupling the sixth gate to the drive signal input, coupling the sixth drain to the seventh gate, the seventh drain to the eighth gate, and the eighth drain to the second gate;
the drive signal input is coupled to the third gate by coupling sixth drain to the fifth gate and coupling the fifth drain to the third gate; and
the drive signal input is coupled to the fourth gate by coupling eighth drain to the fourth gate.
14. The amplifier of claim 13 , wherein for each of the two driver amplifiers the second source, the fourth source, the fifth source and the sixth source, the seventh source, and the eighth source are each coupled to a voltage source and a first capacitor, with the first capacitor coupled to a first ground to provide AC ground through the first capacitor, and wherein the voltage source provides a negative DC bias with respect to the first ground.
15. The amplifier of claim 9 , wherein the first transistor, the second transistor, the third transistor, and the fourth transistor all comprise enhancement mode devices.
16. The amplifier of claim 9 , further comprising:
a combiner with N combiner inputs and a combiner output, wherein each of the combiner inputs is coupled to a different one of the N SMPA branch outputs, and the combiner is configured to combine together the SMPA branch output signal from all of the N SMPA branches to produce, at the combiner output, a combined output signal.
17. The amplifier of claim 16 , wherein the combiner is configured to produce the combined output signal as a signal that is, at any given time, at one of 2*N+1 quantization states.
18. The amplifier of claim 16 , wherein the combiner comprises:
N−1 summing nodes, wherein an output summing node of the N−1 summing nodes is coupled to the combiner output; and
N−1 phase transformers, wherein each phase transformer is coupled to a summing node and is also coupled between SMPA branch outputs of a different set of two adjacent SMPA branches, and wherein the phase transformer is configured to apply a phase delay to the SMPA branch output signal from the SMPA branch that is electrically farther from the output summing node so that the SMPA branch output signals from the two adjacent SMPA branches combine in phase at the summing node to which the phase transformer is coupled.
19. The amplifier of claim 16 , wherein the combiner comprises:
a reconstruction filter coupled to the combiner output, wherein the reconstruction filter is configured to band-pass filter the combined output signal.
20. A method, performed by an amplifier, for amplifying a time varying signal, the method comprising the steps of:
receiving combinations of drive signals by a number, N, of switch-mode power amplifier (SMPA) branches of the amplifier, wherein N is greater than one, and wherein each SMPA branch includes two drive signal inputs, so that the amplifier has a total of 2*N drive signal inputs, and one SMPA branch output, so that the amplifier has a total of N SMPA branch outputs, and where each SMPA branch includes two driver amplifiers, each of the driver amplifiers including;
a first transistor pair, the first transistor pair comprising a first transistor in series with a second transistor, the first transistor comprising an n-type transistor having a first gate, first source and first drain, the second transistor comprising an n-type transistor having a second gate, second source and second drain and wherein the corresponding SMPA branch output is coupled to the first source and the second drain, and wherein one of the corresponding drive signal inputs is coupled to the second gate; and
a second transistor pair, the second transistor pair comprising a third transistor in series with a fourth transistor, the third transistor comprising an n-type transistor having a third gate, third source and third drain, the fourth transistor comprising an n-type transistor having a fourth gate, fourth source and fourth drain, and wherein the one of the corresponding drive signal inputs is coupled to the third gate and the fourth gate, and wherein the first gate is coupled to the third source, and wherein,
in response to receiving a first combination of drive signals at the two drive signal inputs, producing, by each SMPA branch at the SMPA branch output, an SMPA branch output signal at a first voltage level; and
in response to receiving a different second combination of drive signals at the two drive signal inputs, producing, by each SMPA branch at the SMPA branch output, the SMPA branch output signal at a different second voltage level.