Granted Patent B1

US 9,188,640 · App. 14/280,670 · Granted Nov 17, 2015

Abstract

Claims (62)

1. A circuit for generating an output signal based on a first input signal, a clock signal, a test input signal, a launch-off-shift (LOS) signal, a test enable signal, and a reset signal, comprising:

a logic circuit for generating an intermediate output signal at an output terminal thereof based on an inverted clock signal, the test enable signal, a test enable intermediate signal, and the LOS signal, wherein the intermediate output signal comprises the test enable signal OR the LOS signal AND the inverted clock signal AND the test enable intermediate signal;

a multiplexer having a first input terminal for receiving the first input signal, a second input terminal for receiving the test input signal, a select input terminal connected to the output terminal of the logic circuit for receiving the intermediate output signal, and an output terminal for outputting one of the first input and test input signals based on the intermediate output signal; and

a flip-flop circuit having an input terminal connected to the output terminal of the multiplexer for receiving the one of the first input and test input signals as a second input signal, a clock input terminal for receiving the clock signal, a reset terminal for receiving the reset signal, and an output terminal for generating the output signal based on the second input signal, the clock signal, and the reset signal.

2. The circuit of claim 1 , wherein the test enable intermediate signal is generated based on the test input signal and an inverted test enable signal.

3. The circuit of claim 1 , wherein the circuit is a scan flip-flop circuit.

4. The circuit of claim 3 , wherein the scan flip-flop circuit is of a positive-edge triggered D-type flip-flop.

5. A flip-flop circuit for generating an output signal based on an input signal and a clock signal, comprising:

a first transistor having a source terminal for receiving a supply voltage, and a gate terminal for receiving a test enable intermediate signal;

a second transistor having a source terminal connected to a drain terminal of the first transistor, and a gate terminal for receiving the input signal;

a third transistor having a source terminal for receiving the supply voltage, and a gate terminal for receiving an inverted test enable signal;

a fourth transistor having a source terminal connected to a drain terminal of the third transistor, and a gate terminal for receiving a test input signal;

a fifth transistor having a source terminal connected to a drain terminal of the fourth transistor, a gate terminal for receiving the inverted test enable signal, and a drain terminal connected to a drain terminal of the second transistor;

a sixth transistor having a source terminal connected to the drain terminals of the second and fifth transistors, and a gate terminal for receiving the clock signal;

a seventh transistor having a drain terminal connected to a drain terminal of the sixth transistor, and a gate terminal for receiving an inverted clock signal;

an eighth transistor having a drain terminal connected to a source terminal of the seventh transistor, and a gate terminal for receiving the input signal;

a ninth transistor having a drain terminal connected to a source terminal of the eighth transistor, a gate terminal for receiving the inverted test enable signal, and a source terminal connected to ground;

a tenth transistor having a drain terminal connected to the source and drain terminals of the seventh and eighth transistors, respectively, and a gate terminal for receiving the test enable intermediate signal;

an eleventh transistor having a drain terminal connected to a source terminal of the tenth transistor, and a gate terminal for receiving the test input signal;

a twelfth transistor having a drain terminal connected to a source terminal of the eleventh transistor, a gate terminal for receiving the test enable intermediate signal, and a source terminal connected to ground;

a thirteenth transistor having a source terminal connected to the source and drain terminals of the eighth and ninth transistors, respectively, a gate terminal for receiving the inverted test enable signal, and a drain terminal connected to the drain and source terminals of the third and fourth transistors, respectively, wherein the test enable intermediate signal is generated at the drain terminal of the thirteenth transistor;

a fourteenth transistor having a source terminal for receiving the supply voltage, and a gate terminal for receiving the test enable intermediate signal;

a fifteenth transistor having a source terminal for receiving the supply voltage, a gate terminal for receiving the inverted clock signal, and a drain terminal connected to a drain terminal of the fourteenth transistor;

a sixteenth transistor having a source terminal connected the drain terminals of the fourteenth and fifteenth transistors, and a gate terminal for receiving the inverted clock signal;

a seventeenth transistor having a source terminal connected a drain terminal of the sixteenth transistor, and a drain terminal connected to the drain terminals of the sixth and seventh transistors;

an eighteenth transistor having a drain terminal connected to the drain terminal of the seventeenth transistor, and a gate terminal connected to a gate terminal of the seventeenth transistor;

a nineteenth transistor having a drain terminal connected to a source terminal of the eighteenth transistor, a gate terminal for receiving the clock signal, and a source terminal connected to ground;

a twentieth transistor having a source terminal for receiving the supply voltage, and a gate terminal for receiving an inverted reset signal;

a twenty-first transistor having a source terminal connected to a drain terminal of the twentieth transistor, and a gate terminal connected to the drain terminals of the sixth and seventh transistors;

a twenty-second transistor having a drain terminal connected to a drain terminal of the twenty-first transistor, a gate terminal connected to the gate terminal of the twenty-first transistor, and a source terminal connected to ground;

a twenty-third transistor having a drain terminal connected to the drain terminals of the twenty-first and twenty-second transistors, a gate terminal connected to the gate terminal of the twentieth transistor, and a source terminal connected to ground, wherein the drain terminals of the twenty-first through twenty-third transistors are connected to the gate terminals of the seventeenth and eighteenth transistors;

a twenty-fourth transistor having a source terminal for receiving the supply voltage, and a gate terminal connected to the drain terminals of the twenty-first through twenty-third transistors;

a twenty-fifth transistor having a drain terminal connected to a drain terminal of the twenty-fourth transistor, a gate terminal connected to the gate terminal of the twenty-fourth transistor, and a source terminal connected to ground;

a twenty-sixth transistor having a gate terminal for receiving the inverted clock signal, and a source terminal connected to the drain terminals of the twenty-fourth and twenty-fifth transistors;

a twenty-seventh transistor having a gate terminal for receiving the clock signal, a drain terminal connected to the source terminal of the twenty-sixth transistor, and a source terminal connected to a drain terminal of the twenty-sixth transistor;

a twenty-eighth transistor having a source terminal for receiving the supply voltage, and a gate terminal connected to the drain and source terminals of the twenty-sixth and twenty-seventh transistors;

a twenty-ninth transistor having a drain terminal connected to a drain terminal of the twenty-eighth transistor, a gate terminal connected to the gate terminal of the twenty-eighth transistor, and a source terminal connected to ground;

a thirtieth transistor having a source terminal for receiving the supply voltage, and a gate terminal for receiving the clock signal;

a thirty-first transistor having a source terminal connected to a drain terminal of the thirtieth transistor;

a thirty-second transistor having a drain terminal connected to a drain terminal of the thirty-first transistor, and a gate terminal connected to a gate terminal of the thirty-first transistor and to the drain terminals of the twenty-eighth and twenty-ninth transistors;

a thirty-third transistor having a drain terminal connected to a source terminal of the thirty-second transistor, and a gate terminal for receiving the inverted clock signal; and

a thirty-fourth transistor having a drain terminal connected to a source terminal of the thirty-third transistor, a source terminal connected to ground, and a gate terminal for receiving a reset signal;

a thirty-fifth transistor having a source terminal for receiving the supply voltage, a gate terminal for receiving the reset signal, and a drain terminal connected to the drain terminals of the thirty-first and thirty-second transistors and to the gate terminals of the twenty-eight and twenty-ninth transistors;

a thirty-sixth transistor having a source terminal for receiving the supply voltage, and a gate terminal connected to the gate terminals of the twenty-eighth and twenty-ninth transistors; and

a thirty-seventh transistor having a drain terminal connected to a drain terminal of the thirty-sixth transistor, a gate terminal connected to the gate terminal of the thirty-sixth transistor, and a source terminal connected to ground, wherein the output signal is generated at the drain terminals of the thirty-sixth and thirty-seventh transistors.

6. The flip-flop circuit of claim 5 , further comprising:

a thirty-eighth transistor having a source terminal for receiving the supply voltage, and a gate terminal for receiving the reset signal; and

a thirty-ninth transistor having a drain terminal connected to a drain terminal of the thirty-eighth transistor, a gate terminal connected to the gate terminal of the thirty-eighth transistor, and a source terminal connected to ground, wherein the inverted reset signal is generated at the drain terminals of the fortieth and forty-first transistors.

7. The flip-flop circuit of claim 6 , further comprising:

a fortieth transistor having a source terminal for receiving the supply voltage, a gate terminal for receiving a LOS signal, and a drain terminal connected to the drain terminals of the fourteenth and fifteenth transistors;

a forty-first transistor having a source terminal connected to the drain terminal of the fortieth transistor, and a gate terminal for receiving a test enable signal; and

a forty-second transistor having a drain terminal connected to a drain terminal of the forty-first transistor, a gate terminal connected to the gate terminal of the forty-first transistor, and a source terminal connected to ground, wherein the inverted test enable signal is generated at the drain terminals of the forty-first and forty-second transistors, and wherein the drain terminals of the forty-first and forty-second transistors are connected to the source and drain terminals of the eleventh and twelfth transistors, respectively.

8. The flip-flop circuit of claim 7 , further comprising:

a forty-third transistor having a source terminal for receiving the supply voltage, and a gate for receiving an input clock signal (CP); and

a forty-fourth transistor having a drain terminal connected to a drain terminal of the forty-third transistor, a gate terminal connected to the gate terminal of the forty-third transistor, and a source terminal connected to ground, wherein the inverted clock signal is generated at the drain terminals of the forty-third and forty-fourth transistors.

9. The flip-flop circuit of claim 8 , further comprising:

a forty-fifth transistor having a source terminal for receiving the supply voltage, and a gate terminal for receiving the inverted clock signal; and

a forty-sixth transistor having a drain terminal connected to a drain terminal of the forty-fifth transistor, a gate terminal connected to the gate terminal of the forty-fifth transistor, and a source terminal connected to ground, wherein the clock signal is generated at the drain terminals of the forty-fifth and forty-sixth transistors.

10. The flip-flop circuit of claim 9 , wherein the seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fifteenth, eighteenth, nineteenth, twenty-second, twenty-third, twenty-fourth, twenty-seventh, twenty-ninth, thirty-second, thirty-third, thirty-fourth, thirty-seventh, thirty-ninth, forty-second, forty-fourth, and forty-sixth transistors are n-channel metal-oxide semiconductor (NMOS) transistors.

11. The flip-flop circuit of claim 9 , wherein the first, second, third, fourth, fifth, sixth, fourteenth, fifteenth, sixteenth, seventeenth, twentieth, twenty-first, twenty-fourth, twenty-sixth, twenty-seventh, thirtieth, thirty-first, thirty-fifth, thirty-sixth, thirty-eighth, fortieth, forty-first, forty-third, and forty-fifth transistors are p-channel metal-oxide semiconductor (PMOS) transistors.

12. The flip-flop circuit of claim 5 , wherein the flip-flop circuit is of a positive-edge triggered D-type flip-flop.

13. The circuit of claim 5 , wherein the circuit is a scan flip-flop circuit.

Assignments (25)