Semiconductor wafer and method of concurrently testing circuits formed thereon
View Patent ↗A semiconductor wafer has a non-uniform array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring, and each die has a group of bond pads and probe pad coupled to the bond pads. Common electrical interconnects selectively electrically couple together respective probe pads of each of the dies. The common electrical interconnects allow the dies to be tested concurrently before being cut from the wafer.
1. A semiconductor wafer, comprising:
a semiconductor substrate;
an array of identical integrated circuits formed on the substrate, wherein each of the circuits has a plurality of bond pads and a plurality of probe pads including at least first and second probe pads;
a plurality of seal rings, each seal ring enclosing a respective one of the integrated circuits;
a first common electrical interconnect that electrically couples together the first probe pads of the integrated circuits of the array; and
a second common electrical interconnect that electrically couples together the second probe pads of the integrated circuits of the array.
2. The semiconductor wafer of claim 1 , wherein the first and second probe pads are connected to first and second ones of the bond pads.
3. The semiconductor wafer of claim 1 , wherein the seal ring provides a rectangular boundary of four boundary edges and the first and second common electrical interconnects include an interface runner region extending past each respective boundary edge.
4. The semiconductor wafer of claim 3 , wherein each interface runner region is aligned with and coupled to an interface runner region on an adjacent one of integrated circuits.
5. The semiconductor wafer of claim 1 , wherein the first common electrical interconnect electrically couples the first probe pads of the integrated circuits in series.
6. The semiconductor wafer of claim 5 , wherein the first interconnects are on an active surface of each of the integrated circuits.
7. The semiconductor wafer of claim 1 , wherein the first probe pads are at identical locations on each of the integrated circuits.
8. The semiconductor wafer of claim 1 , wherein each of the integrated circuits has at least one probe pad coupled to one of the bond pads, wherein the probe pad is electrically isolated from all other integrated circuits.
9. A method of testing an array of identical fabricated integrated circuits formed on a semiconductor substrate, each of the integrated circuits being enclosed by a respective seal ring, wherein each of the integrated circuits has a group of bond pads and a plurality of probe pads selectively coupled to the bond pads, wherein there are common electrical interconnects that selectively electrically couple together respective ones of the probe pads on each of the integrated circuits, the method comprising:
selectively coupling test probes to the probe pads;
selectively supplying input test patterns to the test probes to thereby concurrently supply the input test patterns to all of the integrated circuits in the array; and
processing output test patterns from the test probes in response to the input test patterns, wherein the output test patterns are received by one or more of the test probes to thereby determine if any of the integrated circuits are faulty.
10. The method of testing of claim 9 , wherein each of the integrated circuits has at least one probe pad coupled to one of the bond pads, wherein the probe pad is electrically isolated from all of the other integrated circuits, and wherein the selectively coupling includes coupling of some of the test probes to the respective probe pads, and wherein the selectively supplying of the input test patterns to the test probes and probe pads is performed concurrently.
11. The method of testing of claim 9 , wherein the processing identifies which, if any, integrated circuits are faulty.
12. The method of testing of claim 9 , wherein the probe pads are at identical locations on each of the integrated circuits.
13. The method of testing of claim 9 , wherein the seal ring provides a rectangular boundary of four boundary edges and the at least one common electrical interconnect includes an interface runner region extending past each respective boundary edge.
14. The method of testing as claimed in claim 13 , wherein each interface runner region is aligned with and coupled to an interface runner region on an adjacent one of the integrated circuits.
15. The method of testing of claim 9 , wherein the probe pads include pads for supplying the input test patterns and at least one pad for providing at least part of the output test patterns.
16. A method of assembling a packaged semiconductor die, the method including:
receiving a semiconductor wafer with an array of identical fabricated integrated circuits formed thereon, wherein each of the integrated circuits is enclosed by a respective seal ring, each of the integrated circuits has a group of bond pads and a plurality of probe pads selectively coupled to the bond pads, wherein there are common electrical interconnects on the wafer that selectively electrically couple together respective ones of the probe pads on each of the integrated circuits, and wherein each of the integrated circuits has at least one die test pad coupled to one of the bond pads, wherein the die test pad is electrically isolated from all of the other integrated circuits;
testing concurrently each of the integrated circuits with input test patterns applied to the probe pads to identify which integrated circuits are fault free;
cutting at least one of the fault free integrated circuits from the semiconductor wafer to provide a single semiconductor die enclosed by one of the seal rings;
electrically connecting the bond pads of the semiconductor die to external package connectors; and
enclosing the semiconductor die in a protective housing.
17. The method of claim 16 , wherein the interconnects are on an active surface of the semiconductor die.
18. The method of claim 16 , wherein the seal ring provides a rectangular boundary of four boundary edges and the interconnects includes an interface runner region extending to a respective boundary edge.
19. The method of claim 16 , wherein the semiconductor die includes more than one die test pad.
20. The method of claim 16 , wherein the probe pads include pads for receiving the input test patterns and the test pad is a pad for providing at least part of an output test pattern.