Granted Patent B2

US 9,899,500 · App. 14/269,825 · Granted Feb 20, 2018

Abstract

Claims (33)

1. A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device, the method comprising:

forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode, the conduction path region having a first conductivity type;

defining a lateral boundary of an active area of the Schottky diode by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type; and

conducting an implant of dopant of the second conductivity type to form a buried JFET gate region in the semiconductor substrate below the conduction path region, the buried JFET gate region being electrically coupled to the well of the device isolating structure;

wherein conducting the implant further forms the device isolating structure in which the Schottky diode is disposed.

2. The method of claim 1 , wherein the implant is configured to form a link region of the device isolating structure, the link region coupling the well and the buried JFET gate region.

3. The method of claim 1 , wherein the buried JFET gate region is configured as a buried device isolating layer of the device isolating structure, the buried device isolating layer extending across an active area of the Schottky diode to meet the well.

4. The method of claim 1 , wherein:

forming the conduction path region comprises conducting a power field-effect transistor (FET) well implant procedure; and

defining the lateral boundary of the active area comprises conducting a logic FET well implant procedure.

5. The method of claim 1 , further comprising conducting a source/drain extension implant procedure to form an upper JFET gate region in the semiconductor substrate, having the second conductivity type, and disposed above the conduction path.

6. The method of claim 1 , further comprising forming an extension region along the conduction path of the Schottky diode, wherein the extension region has the first conductivity type, is disposed adjacent the conduction path region at a surface of the semiconductor substrate, and has a higher dopant concentration level than the conduction path region.

7. The method of claim 6 , wherein forming the extension region comprises conducting a source/drain extension implant procedure.

8. The method of claim 6 , wherein the extension region extends laterally across an entire width of a Schottky barrier junction of the Schottky diode.

9. The method of claim 1 , wherein conducting the implant comprises defining a ring-shaped structure of the buried JFET gate region.

10. A method of fabricating a Schottky diode, the method comprising:

forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode, the conduction path region having a first conductivity type;

forming a well of a device isolating structure in the semiconductor substrate at a lateral boundary of the Schottky diode, the well having a second conductivity type; and

conducting an implant of dopant of the second conductivity type to form a buried gate region in the semiconductor substrate below the conduction path region;

forming first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction at opposite ends of the conduction path;

wherein the well of the device isolating structure is electrically coupled to the second electrode and the buried gate region such that a voltage at the second electrode during operation is applied to the buried gate region to deplete the conduction path region.

11. The method of claim 10 , wherein the buried gate region extends across an active area of the device.

12. The method of claim 10 , further comprising forming a buried device isolating layer of the device isolating structure in the semiconductor substrate, the buried device isolating layer having the second conductivity type, and extending across an active area of the Schottky diode.

13. The method of claim 12 , wherein conducting the implant comprises forming a link region disposed between the device isolating region and the buried device isolating layer such that the buried gate region and the link region have a common dopant profile.

14. The method of claim 10 , further comprising conducting a source/drain extension implant procedure to form an upper gate region in the semiconductor substrate, having the second conductivity type, and disposed above the conduction path.

15. The method of claim 14 , wherein the upper and lower gate regions are laterally spaced from one another.

16. The method of claim 14 , wherein the upper and lower gate regions laterally overlap one another.

17. The method of claim 10 , wherein conducting the implant comprises forming a plurality of buried regions laterally spaced from one another in the semiconductor substrate, having the second conductivity type, disposed below the conduction path region, and electrically coupled to the second electrode, wherein the buried gate region is one of the plurality of buried regions.

18. The method of claim 10 , further comprising forming an isolation trench in the semiconductor substrate adjacent the first electrode, wherein the conduction path region is disposed between the isolation trench and the buried gate region.

19. The method of claim 10 , wherein:

forming the conduction path region comprises conducting a power field-effect transistor (FET) well implant procedure; and

forming the well comprises conducting a logic FET well implant procedure.

20. The method of claim 10 , further comprising conducting a source/drain extension implant to form an extension region along the conduction path of the Schottky diode, wherein the extension region has the first conductivity type, is disposed at the second electrode, and has a higher dopant concentration level than the conduction path region.

Assignments (26)