Memory controller
View Patent ↗A system provides synchronous read data sampling between a memory and a memory controller, which includes an asynchronous FIFO buffer and which outputs a clock and other control signals. An outbound control signal (e.g., read_enable) is used to time-stamp the beginning of a read access using a clock edge counter. The incoming read data is qualified based on the time-stamped value of the read_enable signal plus typical access latency by counting FIFO pops. The system performs correct data sampling irrespective of propagation delays between the controller and memory. The system may be implemented in a System on a Chip (SOC) device having a synchronous communication system.
1. A memory controller for reading data from a memory, wherein the memory has an access latency of ‘L’ memory clock cycles, where L is a positive integer, the controller comprising:
a FIFO (first in first out) buffer for receiving data read from the memory;
a clock module for providing a memory clock signal to the memory and to the FIFO buffer;
a control signal generation module for asserting a control signal and applying said control signal to the memory;
a counter for determining an assertion time of said control signal as a function of a number ‘N’ of cycles of the memory clock signal, where N is a positive integer; and
a data sampling module coupled to the counter and to the FIFO buffer for sampling an output of the FIFO buffer at a point in time that is a function of N and L.
2. The memory controller of claim 1 , wherein data read from the memory is clocked into the FIFO by the memory clock signal and clocked out of the FIFO as a sequence of pops.
3. The controller of claim 2 , wherein ‘N’ is the number of system clock edges, counted by the counter, that have elapsed from a start of the memory clock signal until assertion of said control signal.
4. The controller of claim 3 , wherein the data sampling module has stored therein the access latency ‘L’ and receives the number ‘N’ from the counter and counts a number of FIFO pops output from the FIFO buffer and samples the subsequent FIFO pop after L+N pops have been counted.
5. The controller of claim 1 , wherein the FIFO is an asynchronous FIFO.
6. The controller of claim 1 , wherein the control signal comprises a read enable signal.
7. A method for reading data from a memory using a controller, wherein the controller includes a FIFO (first in first out) buffer having an input for receiving data read from the memory, and an output, and the memory has an access latency of ‘L’ memory clock cycles associated therewith, where L is a positive integer, the method comprising:
applying a memory clock signal to the memory and the FIFO buffer;
asserting a control signal and applying said control signal to the memory;
recording a time of assertion of the control signal as a function of a number, N, of cycles of the memory clock signal, where N is a positive integer; and
sampling the output of the FIFO buffer at a point in time that is a function of N and L.
8. A processing system, comprising:
a memory for storing data and having an access latency of ‘L’ memory clock cycles associated therewith, where L is a positive integer; and
a controller, operably coupled to the memory and including a FIFO (first in first out) buffer having an input coupled to an output of the memory for receiving data read from the memory,
wherein the controller provides a memory clock signal to the memory and to the FIFO buffer, asserts a control signal and applies said control signal to the memory, records a time of assertion of the control signal as a function of a number, N, of cycles of the memory clock signal, where N is a positive integer, and samples the output of the FIFO buffer at a point in time that is a function of N and L.
9. The system of claim 8 , wherein the system is implemented in a system on a chip (SOC).