System and method for testing address-swap faults in multiport memories
View Patent ↗A system method of detecting address-swap faults in a multiport memory as described herein includes minimum testing for inversion faults and bit-swap faults for each port of the multiport memory. Different test types may be performed for inversion and bit-swap including pass/fail, and diagnostic testing for locating faulty ports. Pass/fail testing may be used for identifying whether the IC is good or bad, and additional diagnostic testing using additional cycles may be used for disabling faulty ports or correcting inverted address bits. The test method may be implemented as a function test or as a memory built-in self-test. The test method may be used during manufacturing test or during function design verification.
1. A method of detecting address-swap faults in a multiport memory, comprising:
initializing each addressable location with a first data value via a first port of the multiport memory;
writing a second data value to a first address via the first port, wherein the second data value is different from the first data value; and
for every port of the multiport memory other than the first port:
reading a stored data value at the first address via the port, and
failing the port when the stored data value is not equal to the second data value.
2. The method of claim 1 , wherein when the multiport memory includes more than two ports and when every port other than the first port fails, further comprising failing the first port and passing every other port.
3. The method of claim 1 , further comprising storing a fail indication for each failed port in a pass/fail list.
4. The method of claim 1 , further comprising:
re-initializing each addressable location with the first data value; and
for each address according to at least one Walsh Hadamard Code:
writing the second data value to the address via the first port, and
after said writing the second data value to the address via the first port, for every port other than the first port:
reading a stored data value at the address via the port, and
failing the port when the stored data value is not equal to the second data value.
5. The method of claim 4 , wherein when the multiport memory includes more than two ports and when every port other than the first port fails, further comprising failing the first port and passing every other port.
6. The method of claim 4 , further comprising storing a fail indication for each failed port in a bit-swap pass/fail list.
7. The method of claim 4 , wherein each address according to the at least one Walsh Hadamard Code comprises a repeating sequence of a number of logic zero values followed by the same number of logic one values.
8. The method of claim 4 , wherein the Walsh Hadamard Code is according to a function WM(m), in which m is a positive integer index value that identifies a number r of times each logic value is repeated in which r=2 (m-1) , and in which m is incremented from one to m=LOG 2 (n) in which n is a number of address bits.
9. A method of detecting address-swap faults in a multiport memory, comprising:
initializing each addressable location of the multiport memory with a first data value; and
for each address according to at least one Walsh Hadamard Code:
writing a second data value to the address via a first port of the multiport memory; and
after said writing the second data value to the address via the first port, for every port other than the first port:
reading a stored data value at the address via the port, and
failing the port when the stored data value is not equal to the second data value.
10. The method of claim 9 , wherein when the multiport memory includes more than two ports and when every port other than the first port fails, further comprising failing the first port and passing every other port.
11. The method of claim 9 , further comprising storing a fail indication for each failed port in a bit-swap pass/fail list.
12. The method of claim 9 , wherein each address according to the at least one Walsh Hadamard Code comprises a repeating sequence of a number of logic zero values followed by the same number of logic one values.
13. The method of claim 9 , wherein the Walsh Hadamard Code is according to a function WM(m), in which m is a positive integer index value that identifies a number r of times each logic value is repeated in which r=2 (m-1) , and in which m is incremented from one to m=LOG 2 (n) in which n is a number of address bits.
14. A memory system, comprising:
a memory including a multiport memory; and
a memory test system that detects address-swap faults in said multiport memory, comprising:
a pattern generator that generates test patterns;
an address block that provides addresses to ports of said multiport memory;
a read/write control block that controls read and write operations of each of said ports of said multiport memory; and
a comparator that compares a data input with a data output for each of said ports of said multiport memory; and
wherein said memory test system is operative to:
initialize each addressable location of said multiport memory with a first data value via a first port;
write a second data value to a first address via said first port, wherein said second data value is different from said first data value;
for every port other than said first port of the multiport memory:
read a stored data value at said first address via said port, and
fail said port when said stored data value is not equal to said second data value.
15. The memory system of claim 14 , wherein said multiport memory and said memory test system are incorporated on a system-on-a-chip configuration.
16. The memory system of claim 14 , wherein when said multiport memory includes more than two ports, said memory test system is further configured to fail said first port and pass said every other port when said memory test system initially determines that said every port other has failed.
17. The memory system of claim 14 , wherein when said multiport memory includes more than two ports, further comprising:
a pass/fail list stored in said memory; and
wherein said memory test system is further configured to:
store a pass or fail indication in said pass/fail list,
scan said pass/fail list to identify ports indicated as failed, and
when said every port other than said first port is indicated as failed in said pass/fail list, indicating that said first port has failed and indicating that said every other port has passed in said pass/fail list.
18. The memory system of claim 14 , wherein said memory test system is further operative to:
re-initialize each addressable location with said first data value; and
for each address according to at least one Walsh Hadamard Code:
write said second data value to said address via said first port, and
after writing said second data value to said address via said first port, for every port other than said first port:
read a stored data value at said address via said port, and
fail said port when said stored data value is not equal to said second data value.
19. The memory system of claim 18 , wherein when said multiport memory includes more than two ports and when every port other than said first port fails, said memory test system is further configured to fail said first port and pass said every other port.
20. The memory system of claim 18 , wherein when said multiport memory includes more than two ports, further comprising:
a bit-swap pass/fail list; and
wherein said memory test system is further configured to:
store a pass or fail indication in said bit-swap pass/fail list,
scan said bit-swap pass/fail list to identify ports indicated as failed, and
when said every port other than said first port is indicated as failed in said bit-swap pass/fail list, indicating that said first port has failed and indicating that said every other port has passed in said bit-swap pass/fail list.