Encoder, decoder and semiconductor device including the same
A semiconductor device may include a first encoding unit configured to encode first data into an anti-drift code, and a second encoding unit configured to add parity information to the anti-drift code.
1. A semiconductor device comprising:
a first encoding unit configured to encode first data into an anti-drift code; and
a second encoding unit configured to add parity information to the anti-drift code,
wherein the first data may be recovered from a data including the anti-drift code and a drift noise generated while the anti-drift code is stored in a semiconductor memory device.
2. The semiconductor device of claim 1 , wherein the anti-drift code comprises M different symbols, each of which includes N symbols,
wherein M and N are natural numbers.
3. The semiconductor device of claim 2 , wherein binary data corresponding to the symbol comprises a gray code.
4. The semiconductor device of claim 2 , wherein the second encoding unit analyzes the anti-drift code in units of a symbol to add the parity information.
5. The semiconductor device of claim 1 , wherein the second encoding unit analyzes the anti-drift code in units of a bit to add the parity information.
6. The semiconductor device of claim 5 , wherein when the number of bits of an added parity information is an odd number of bits, the second encoding unit adds one arbitrary bit to the parity information such that the number of bits of the parity information becomes an even number of bits.
7. The semiconductor device of claim 1 , wherein the semiconductor device further receives second data which are not converted into an anti-drift code, and the second encoding unit adds the parity information to the second data and the anti-drift code.
8. A semiconductor device which decodes an input data including an anti-drift code obtained by encoding first data, parity information on the anti-drift code, and drift noise, comprising:
a first decoding unit configured to recover the anti-drift code from the input data and recover the parity information by referring to the recovery information;
a second decoding unit configured to output an error-corrected anti-drift code from the recovered parity information and the recovered anti-drift code; and
a third decoding unit configured to decode the error-corrected anti-drift code and output the first data.
9. The semiconductor device of claim 8 , wherein the anti-drift code comprises M different symbols, each of which includes N symbols,
wherein M and N are natural numbers.
10. The semiconductor device of claim 9 , wherein binary data corresponding to the symbol comprises a gray code.
11. The semiconductor device of claim 9 , wherein the parity information is obtained by analyzing the anti-drift code in units of symbol.
12. The semiconductor device of claim 8 , wherein the parity information is obtained by analyzing the anti-drift code in units of bit.
13. The semiconductor device of claim 8 , wherein the input data further comprises second data which are not encoded into an anti-drift code and drift noise of the second data.
14. The semiconductor device of claim 13 , wherein the first decoding unit recovers the second data by referring to the recovery information, and the second decoding unit outputs the error-corrected anti-drift code and the error-corrected second data by referring to the parity information.
15. A semiconductor device comprising:
an encoder configured to encode data provided from a host into an anti-drift code, add parity information to the anti-drift code, and output the anti-drift code and the parity information; and
a decoder configured to recover the anti-drift code and the parity information from information outputted from a semiconductor memory device, generate the error-corrected anti-drift code using the recovered parity information, and decode and output the anti-drift code,
wherein the data from the host may be recovered from the anti-drift code and a drift noise generated while the anti-drift code is stored in the semiconductor memory device.
16. The semiconductor device of claim 15 , wherein the anti-drift code comprises M different symbols, each of which includes N k symbols,
wherein M, k, and N k are natural numbers, and
wherein k is greater than or equal to one and M is greater than or equal to k (1≦k ≦M).
17. The semiconductor device of claim 16 , wherein binary data corresponding to the symbol comprises a gray code.
18. The semiconductor device of claim 15 , wherein the encoder comprises:
a first encoding unit configured to encode first data into an anti-drift code; and
a second encoding unit configured to add parity information to the anti-drift code.
19. The semiconductor device of claim 18 , wherein the decoder comprises:
a first decoding unit configured to recover the anti-drift code from the output information and recover the parity information by referring to the recovery information;
a second decoding unit configured to output an error-corrected anti-drift code from the recovered parity information and the recovered anti-drift code; and
a third decoding unit configured to decode the error-corrected anti-drift code and output the first data.
20. The semiconductor device of claim 18 , wherein the second encoding unit adds the parity information to the anti-drift code and second data which are not encoded into an anti-drift code, and
the first decoding unit further recovers the second data by referring to the recovery information, and the second decoding unit further outputs the error-corrected second data from the parity information.
21. The semiconductor device of claim 18 , wherein when a number of bits of an added parity information is an odd number of bits, the second encoding unit adds one arbitrary bit to the parity information such that the number of bits of the parity information becomes an even number of bits.
22. A semiconductor memory device comprising:
a memory cell array;
an encoder configured to encode data provided from a memory control device into an anti-drift code, add parity information to the anti-drift code, and provide the anti-drift code to the memory cell array; and
a decoder configured to recover the anti-drift code and the parity information from information outputted from the memory cell array, generate the error-corrected drift code using the recovered parity information, and decode and output the drift code,
wherein the data provided from the memory control device may be recovered from the anti-drift code and a drift noise generated while the anti-drift code is stored in the semiconductor memory device.
23. The semiconductor device of claim 22 , wherein the anti-drift code comprises M different symbols, each of which includes N includes N k symbols,
wherein M, k, and N k are natural numbers, and
wherein k is greater than or equal to one and M is greater than or equal to k (1≦k≦M).
24. The semiconductor device of claim 23 , wherein binary data corresponding to the symbol comprises a gray code.
25. The semiconductor device of claim 22 , wherein the encoder comprises:
a first encoding unit configured to encode first data into an anti-drift code; and
a second encoding unit configured to add parity information to the anti-drift code.
26. The semiconductor device of claim 25 , wherein the decoder comprises:
a first decoding unit configured to recover the anti-drift code from the output information and recover the parity information by referring to the recovery information;
a second decoding unit configured to output an error-corrected anti-drift code from the recovered parity information and the recovered anti-drift code; and
a third decoding unit configured to decode the error-corrected anti-drift code and output the first data.
27. The semiconductor device of claim 26 , wherein the second encoding unit adds the parity information to the anti-drift code and second data which are not encoded into an anti-drift code, and
the first decoding unit further recovers the second data by referring to the recovery information, and the second decoding unit further outputs the error-corrected second data from the parity information.