Flash memory cells having trenched storage elements
View Patent ↗An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.
1. A method of fabricating a semiconductor memory cell having at least two charge storage elements, the method comprising:
forming a first trench and an adjacent second trench in a semiconductor substrate, said first and second trenches each defining a first sidewall and a second sidewall respectively;
forming a first charge storage element on said first sidewall of said first trench;
forming a second charge storage element on said second sidewall of said second trench;
forming a first source/drain region in the substrate;
forming an oxide layer extending into and substantially contacting an entire upper surface of an upper region of the first source/drain region;
forming a first oxide layer on the first sidewall of the first trench, wherein the first oxide layer is formed using thermal oxidation and wherein during the thermal oxidation, the first source/drain region diffuses, forming another source/drain region larger than the source/drain region; and
forming a charge storage layer on the first oxide layer.
2. The method as recited in claim 1 wherein said forming of said first charge storage element comprises:
forming a second oxide layer on said charge storage layer.
3. The method as recited in claim 2 wherein said charge storage layer is selected from the group consisting of silicon nitride, silicon rich nitride, polycrystalline silicon, and high-K material.
4. The method as recited in claim 1 further comprising forming a word line in contact with said first charge storage element and said second charge storage element.
5. The method as recited in claim 1 further comprising:
forming a hard mask over said oxide layer; and
removing portions of said hard mask corresponding to locations where said first and second trenches are to be formed.
6. The method as recited in claim 1 wherein said first trench has a depth in a range of 100-1000 angstroms.
7. The method as recited in claim 1 further comprising:
forming a second source/drain region in said substrate, said first source/drain region and said second source/drain region formed substantially under said first trench and said second trench in said semiconductor substrate, respectively.
8. The method as recited in claim 1 wherein said forming of said first source/drain region comprises:
forming an offset spacer on said first sidewall of said first trench;
implanting said first source/drain region in said substrate; and
removing said offset spacer.