IP Library Granted Patent US 10,062,426
Granted Patent B2
US 10,062,426 · App. 14/260,940 · Granted Aug 28, 2018

Field effect transistor constructions with gate insulator having local regions radially there-through that have different capacitance at different circumferential locations relative to a channel core periphery

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Quick Facts
Patent No.
US 10,062,426
App. No.
14/260,940
Granted
Aug 28, 2018
Kind
B2
Abstract

A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

Claims (27)

1. A field effect transistor construction, comprising:

a semiconductive channel core having four radially outermost surfaces that are straight along at least a majority of their respective circumferential lengths;

a source/drain region at opposite ends of the channel core, the channel core comprising a minimum channel length there-through from an edge of one of the source/drain regions to an edge of the other source/drain region;

a gate proximate a periphery of the channel core;

a gate insulator between the gate and the channel core over each of the four surfaces, the gate insulator over a first two of diametrically opposed of the four surfaces being radially thinner along all of the minimum channel length than over a second two of diametrically opposed of the four surfaces along all of the minimum channel length; and

the radially thinner gate insulator providing greater local capacitance than does the gate insulator over said second two.

2. A field effect transistor construction, comprising:

a semiconductive channel core;

a source/drain region at opposite ends of the channel core, the channel core comprising a minimum channel length there-through from an edge of one of the source/drain regions to an edge of the other source/drain region;

a gate proximate a periphery of the channel core, the gate completely surrounding the channel core; and

a gate insulator between the gate and the channel core, the gate insulator completely surrounding the channel core, the gate insulator comprising two pairs of two diametrically opposed local regions extending radially through the gate insulator that individually extend along all of the minimum channel length at different circumferential locations relative to the channel core periphery, the two pairs having different collective capacitance along all of the minimum channel length, the gate insulator comprising only two of said pairs.

3. A field effect transistor construction comprising:

a semiconductive channel core;

a source/drain region at opposite ends of the channel core, the channel core comprising a minimum channel length there-through from an edge of one of the source/drain regions to an edge of the other source/drain region;

a gate proximate a periphery of the channel core;

a gate insulator between the gate and the channel core, the gate insulator having local regions radially there-through that individually extend along all of the minimum channel length and that have different capacitance at different circumferential locations along all of the minimum channel length relative to the channel core periphery; and

ferroelectric material radially inward of the gate and conductive material radially inward of the ferroelectric material, the ferroelectric material and the conductive material being radially outward of the gate insulator.

4. The construction of claim 3 wherein the gate insulator is devoid of ferroelectric material.

5. A field effect transistor construction, comprising:

a semiconductive channel core;

a source/drain region at opposite ends of the channel core, the channel core comprising a minimum channel length there-through from an edge of one of the source/drain regions to an edge of the other source/drain region;

a gate construction proximate a periphery of the channel core, the gate construction comprising:

outer conductive material proximate the channel core periphery;

outer ferroelectric material proximate the channel core periphery radially inward of the outer conductive material;

inner conductive material proximate the channel core periphery radially inward of the outer ferroelectric material; and

inner dielectric radially between the inner conductive material and the channel core, the inner dielectric having local regions radially there-through of different radial thickness that individually extend along all of the minimum channel length at different circumferential locations relative to the channel core periphery.

6. The construction of claim 5 wherein the local regions having different radial thicknesses have different capacitance relative one another.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2014
From: KARDA, KAMAL M.; MOULI, CHANDRA; RAMASWAMY, DURAI VISHAK NIRMAL; GEALY, F. DANIEL
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032750/0945 →
Cited By (3)
US 12,402,321 US 12,408,388 US 12,532,478