Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors
View Patent ↗A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. A gate construction of the transistor comprises inner dielectric extending along the channel top and laterally along the channel sidewalls. Inner conductive material is elevationally and laterally outward of the inner dielectric and extends along the channel top and laterally along the channel sidewalls. Outer ferroelectric material is elevationally outward of the inner conductive material and extends along the channel top. Outer conductive material is elevationally outward of the outer ferroelectric material and extends along the channel. Other constructions and methods are disclosed.
1. A method of forming a plurality of ferroelectric field effect transistors, comprising:
forming a plurality of trenches into semiconductive material, the trenches being parallel and longitudinally elongated relative to horizontal;
forming inner dielectric over sidewalls of the trenches and over semiconductive material that is between the trenches;
forming first inner conductive material over the inner dielectric, bases of the trenches, the trench sidewalls, and the semiconductive material that is between the trenches, the first inner conductive material being continuous within and between the trenches at least in a direction orthogonal to a horizontal longitudinal running direction of the parallel trenches;
forming second inner conductive material over and electrically coupled to the first inner conductive material; the second inner conductive material being formed elevationally thicker over the semiconductive material that is between the trenches than any that is formed elevationally centrally over the trench bases;
in at least one common etching step, anisotropically etching both:
a) the first inner conductive material from over the trench bases to isolate the first inner conductive material from being continuous over the individual trench bases; and
b) the second inner conductive material that is elevationally over the semiconductive material that is between the trenches;
after the etching, forming outer ferroelectric material elevationally over the first inner conductive material that is over the semiconductive material that is between the trenches;
forming outer conductive material elevationally over the outer ferroelectric material; and
forming source/drain regions in the semiconductive material that is between the trenches on opposing sides of the first inner conductive material that overlies the semiconductive material that is between the trenches.
2. The method of claim 1 wherein said forming inner dielectric also forms the inner dielectric elevationally over the trench bases, said forming first inner conductive material also forms the first inner conductive material elevationally over the inner dielectric that is over the trench bases, said common etching step exposing the inner dielectric that is over the trench bases.
3. The method of claim 1 wherein said forming second inner conductive material forms the second inner conductive material elevationally over the trench bases.
4. The method of claim 1 wherein,
said forming first inner conductive material is also continuous within and between the trenches in the horizontal longitudinal running direction of the parallel trenches; and comprising:
etching through the first inner conductive material within and between the trenches to form lines of the first inner conductive material that run orthogonal to the longitudinal running direction of the parallel trenches.
5. The method of claim 1 wherein said at least one common etching step leaves some of the second inner conductive material elevationally over the first inner conductive material between the trenches.
6. The method of claim 1 wherein said forming second inner conductive material also forms the second inner conductive material to run continuously over the semiconductive material between the trenches at least in a direction parallel to the longitudinal running direction of the parallel trenches.
7. The method of claim 6 comprising etching through both of the first inner conductive material and the second inner conductive material to isolate the first inner conductive material and the second inner conductive material from being continuous over the semiconductive material between the trenches.
8. The method of claim 7 wherein said etching through both of the first inner conductive material and the second inner conductive material occurs before said at least one common etching step.
9. The method of claim 7 wherein said etching through both of the first inner conductive material and the second inner conductive material occurs after said at least one common etching step.
10. The method of claim 1 wherein said forming second inner conductive material also forms the second inner conductive material to run continuously over the trench bases, the trench sidewalls, and the semiconductive material between the trenches at least in the direction orthogonal to the longitudinal running direction of the parallel trenches.
11. The method of claim 10 wherein said at least one common etching step leaves some of the second inner conductive material laterally along the trench sidewalls.
12. The method of claim 11 wherein said at least one common etching step leaves some of the second inner conductive material elevationally over the first inner conductive material between the trenches.
13. The method of claim 1 comprising forming dielectric fill material within the trenches over the trench bases and over the first inner conductive material that is along the trench sidewalls before said forming outer ferroelectric material.
14. The method of claim 1 wherein said anisotropic common etching is conducted in the absence of masking at least within an entirely of an array region of the transistors being formed.