Granted Patent B2

US 9,768,181 · App. 14/263,610 · Granted Sep 19, 2017

Abstract

Claims (77)

1. A memory cell, comprising:

a buried recessed access device (BRAD) formed in a substrate;

a ferroelectric capacitor formed on the BRAD; and

a first conductive contact formed directly on an active region corresponding to the BRAD, wherein the first conductive contact connects a first electrode of the ferroelectric capacitor to a first electrode of a capacitor of a second cell;

a second conductive contact that connects a second electrode of the second cell to an electrode of a third cell, wherein a ferroelectric material of a ferroelectric capacitor of the second cell directly contacts the second conductive contact.

2. The memory cell of claim 1 , wherein the ferroelectric capacitor is a container capacitor having the ferroelectric material formed therein.

3. The memory cell of claim 2 , wherein the ferroelectric material is formed via atomic layer deposition.

4. The memory cell of claim 2 , wherein the ferroelectric material is formed on sidewalls of an electrode material in a container of the container capacitor.

5. The memory cell of claim 4 , wherein a height of the container is not less than about 10 kilo-angstroms and a diameter of the container is not greater than about 600 angstroms.

6. The memory cell of claim 1 , wherein a gate of the BRAD is formed between a first source/drain region and a second source/drain region corresponding to the BRAD, and wherein the gate is formed below an upper surface of at least one of the first and the second source/drain region.

7. The memory cell of claim 6 , wherein a bottom electrode of the ferroelectric capacitor is coupled to the first source/drain region, and wherein a top electrode of the ferroelectric capacitor is coupled to the second source/drain region.

8. The memory cell of claim 1 , wherein the second conductive contact is formed at least partially on the second source/drain region and at least partially on a dielectric material corresponding to an isolation region between the memory cell and the second memory cell.

9. The memory cell of claim 1 , wherein the ferroelectric capacitor is on pitch with the BRAD.

10. The memory cell of claim 1 , wherein the memory cell achieves a 4F 2 architecture with F being a feature size corresponding to the memory cell.

11. The memory cell of claim 1 , wherein the ferroelectric capacitor is coupled in series with a ferroelectric capacitor of the second memory cell.

12. A method for forming a memory cell, comprising:

forming a buried recessed access device (BRAD) in a substrate, wherein a gate of the BRAD is formed below an upper surface of a first source/drain region and below an upper surface of a second source/drain region corresponding to the BRAD;

forming a first electrode contact on a capping material of the BRAD and on the first source/drain region;

forming a container corresponding to a ferroelectric capacitor on the first electrode contact, wherein the first electrode contact connects the ferroelectric capacitor to a ferroelectric capacitor of a second memory cell;

forming a bottom electrode of the ferroelectric capacitor in the container and on the first electrode contact;

forming a ferroelectric material in the container;

forming a top electrode in the container; and

forming at least a portion of a conductive pillar on the second source/drain region, wherein the conductive pillar is coupled to the top electrode via a second electrode contact, wherein the second electrode contact connects a top electrode of the second memory cell to an electrode of a third cell, and wherein a ferroelectric material of a ferroelectric capacitor of the second cell directly contacts the second conductive contact.

13. The method of claim 12 , comprising forming the ferroelectric capacitor on pitch with the BRAD.

14. The method of claim 12 , comprising:

forming an isolation region between the BRAD and a BRAD of an adjacent memory cell; and

forming at least a portion of the conductive pillar on a dielectric material corresponding to the isolation region.

15. The method of claim 12 , further comprising forming the ferroelectric capacitor in series with respective ferroelectric capacitors of a number of additional memory cells between a first conductive line and a second conductive line.

16. The method of claim 12 , wherein the container has an aspect ratio of at least 20:1, and wherein forming the ferroelectric material in the container comprises depositing at least one of:

a lead zirconate titanate (PZT) material;

a strontium bismuth tantalate (SBT) material;

a hafnium oxide based material; and

a zirconium oxide based material.

17. The method of claim 16 , wherein the hafnium oxide based material and the zirconium oxide based material are doped with at least one of: silicon (Si), aluminum (Al), germanium (Ge), magnesium (Mg), calcium (Ca), strontium (Sr), niobium (Nb), yttrium (Y), barium (Ba), titanium (Ti), and/or a combination thereof.

18. A ferroelectric random access memory (FeRAM), comprising:

a first plurality of ferroelectric capacitors coupled in series between a first conductive line and a second conductive line; and

a second plurality of ferroelectric capacitors coupled in series between the first conductive line and a third conductive line;

wherein each ferroelectric capacitor of the first and second plurality of ferroelectric capacitors is coupled to a respective buried recessed access device (BRAD) having a gate electrode formed therebeneath;

wherein a first ferroelectric capacitor of the first plurality is adjacent to a second ferroelectric capacitor of the first plurality, and the second ferroelectric capacitor of the first plurality is adjacent to a third ferroelectric capacitor of the first plurality, wherein the first ferroelectric capacitor is connected to the second ferroelectric capacitor by a first conductive contact, wherein the second ferroelectric capacitor is connected to the third ferroelectric capacitor by a second conductive contact, and wherein a ferroelectric material of the second ferroelectric capacitor directly contacts the second conductive contact.

19. The FeRAM of claim 18 , wherein each of the first plurality of ferroelectric capacitors are formed in a container and include:

a bottom electrode formed on sidewalls of the container and on a bottom electrode contact;

a ferroelectric material formed in the container and on sidewalls of the bottom electrode; and

a top electrode formed in the container and on sidewalls of the ferroelectric material, the top electrode coupled to a source/drain region of the corresponding BRAD via a conductive pillar, wherein at least a first portion of the conductive pillar is formed on a dielectric material of an isolation region separating BRADs corresponding to the first plurality of ferroelectric capacitors and BRADs corresponding to the second plurality of ferroelectric capacitors.

20. The FeRAM of claim 19 , wherein the first conductive line is a plate line, the second conductive line is a bit line, and the third conductive line is a different bit line.

21. The FeRAM of claim 18 , wherein at least one of the first plurality of ferroelectric capacitors comprises a ferroelectric storage material selected from the group including:

lead zirconate titanate (PZT); and

strontium bismuth tantalate (SBT);

a hafnium oxide based material; and

a zirconium oxide based material.

22. The FeRAM of claim 18 , wherein the first plurality of ferroelectric capacitors include at least four ferroelectric capacitors.

23. The FeRAM of claim 18 , wherein the first plurality of ferroelectric capacitors include at least eight ferroelectric capacitors.

24. The FeRAM of claim 18 , further comprising:

a first select device configured to selectively couple the first plurality of ferroelectric capacitors to the first conductive line; and

a second select device configured to selectively couple the second plurality of ferroelectric capacitors to the first conductive line.

25. A method for forming a ferroelectric random access memory (FeRAM), comprising:

forming a first plurality of buried recessed access devices (BRAD) corresponding to a respective first plurality of memory cells;

forming a first plurality of ferroelectric capacitors on the first plurality of BRADs; and

forming a second plurality of BRADs corresponding to a respective second plurality of memory cells; and

forming a second plurality of ferroelectric capacitors on the second plurality of BRADs;

wherein the first plurality of ferroelectric capacitors are coupled in series with each other between a first conductive line and a second conductive line; and

wherein the second plurality of ferroelectric capacitors are coupled in series with each other between the first conductive line and a third conductive line; and

wherein a first ferroelectric capacitor of the first plurality is adjacent to a second ferroelectric capacitor of the first plurality, and the second ferroelectric capacitor of the first plurality is adjacent to a third ferroelectric capacitor of the first plurality, wherein the first ferroelectric capacitor is connected to the second ferroelectric capacitor by a first conductive contact, wherein the second ferroelectric capacitor is connected to the third ferroelectric capacitor by a second conductive contact, and wherein a ferroelectric material of the second ferroelectric capacitor directly contacts the second conductive contact.

26. The method of claim 25 , wherein forming the first plurality of BRADS comprises:

forming a gate of the plurality of BRADS with at least one of:

a polysilicon material;

a titanium nitride; and

a tantalum nitride.

27. The method of claim 25 , wherein forming the first plurality of BRADS comprises:

forming a gate of the BRADS beneath a surface of a substrate.

28. The method of claim 25 , wherein forming the first plurality of ferroelectric capacitors comprises:

forming a number of conductive contacts on the first plurality of BRADS;

depositing a dielectric material on the conductive contacts;

etching a number of containers in the dielectric material;

depositing a first conductive material in the number of containers;

depositing, via atomic layer deposition, a ferroelectric material on the first conductive material; and

depositing a second conductive material in the number of containers.

29. The method of claim 28 , wherein the first conductive material acts as a bottom electrode of the ferroelectric capacitor and the second conductive material acts as a top electrode of the ferroelectric capacitor.

Assignments (8)