IP Library › Granted Patent US 9,312,265
Granted Patent B2
US 9,312,265 · App. 14/263,634 · Granted Apr 12, 2016

Apparatus for high speed ROM cells

Inventor: Jhon-Jhy Liaw (Zhudong Township, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L27/11213G11C5/06G11C11/412G11C17/08H01L27/1124H01L29/785G11C5/02G11C5/063H01L27/0207H01L2029/7858
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Quick Facts
Patent No.
US 9,312,265
App. No.
14/263,634
Granted
Apr 12, 2016
Kind
B2
Abstract

A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is coupled to a first VSS line and a second VSS line formed in a first interconnect layer, wherein the second VSS line is electrically coupled to the first VSS line, and wherein the second VSS line is of a direction orthogonal to a direction of the first VSS line. The ROM cell further comprises a first bit line formed in the first interconnect layer, wherein the first bit line is formed in parallel with the second VSS line and a second bit line formed in the first interconnect layer, wherein the second bit line is formed in parallel with the second VSS line.

Claims (75)

1. A device comprising:

a fin structure over a substrate;

a gate wrapping the fin structure around three sides of the fin structure;

a first VSS line in a contact layer overlying the substrate;

a first bit line in a first interconnect layer overlying the contact layer;

a second bit line in the first interconnect layer, wherein the second bit line is in parallel with the first bit line;

a word line in a second interconnect layer overlying the first interconnect layer; and

a word line strap structure comprising:

a gate contact in the contact layer;

a first via in the first interconnect layer:

a first metal line in the first interconnect layer, wherein the first metal line is over the first via; and

a second via in the second interconnect layer, wherein the word line is over the second via.

2. The device of claim 1 , wherein:

the fin structure comprises a drain, a source and a channel coupled between the drain and the source.

3. The device of claim 2 , wherein:

the source is connected to the first VSS line; and

the drain is coupled to the first bit line through a coding layer.

4. The device of claim 3 , wherein:

the coding layer is formed by a first contact and a first via, and wherein the first via is in the first interconnect layer and underneath the first bit line.

5. The device of claim 1 , further comprising:

a second VSS line in the first interconnect layer, wherein the second VSS line is parallel with the first bit line.

6. The device of claim 5 , further comprising:

a third VSS line in the second interconnect layer, wherein the third VSS line is electrically coupled to the second VSS line.

7. The device of claim 6 , wherein:

the third VSS line is in parallel with the word line.

8. A memory cell comprising:

a memory transistor comprising a drain, a source, a gate, and a channel coupled between the drain and the source;

a first VSS line in a contact layer overlying a substrate;

a first bit line in a first interconnect layer overlying the contact layer;

a second bit line in the first interconnect layer, wherein the second bit line is in parallel with the first bit line;

a second VSS line in the first interconnect layer, wherein the second VSS line is in parallel with first bit line;

a word line in a second interconnect layer overlying the first interconnect layer;

a third VSS line in the second interconnect layer, wherein the third VSS line is in parallel with the word line; and

a word line strap structure coupled between the gate and the word line.

9. The memory cell of claim 8 , wherein the word line strap structure comprises:

a gate contact in the contact layer;

a first via in the first interconnect layer:

a first metal line in the first interconnect layer, wherein the first metal line is over the first via; and

a second via in the second interconnect layer, wherein the word line is over the second via.

10. The memory cell of claim 8 , wherein:

the second VSS line is electrically coupled to the first VSS line through a first via in the first interconnect layer.

11. The memory cell of claim 8 , wherein:

the third VSS line is electrically coupled to the second VSS line.

12. The memory cell of claim 8 , wherein:

the drain is electrically coupled to the first bit line; and

the source is electrically coupled to the first VSS line.

13. The memory cell of claim 8 , wherein:

the word line is of a direction orthogonal to a direction of the first bit line.

14. An apparatus comprising:

a plurality of interconnect structures over a substrate;

a gate in a contact layer over the substrate;

a first VSS line in the contact layer;

a first bit line in a first interconnect layer over the contact layer;

a second bit line in the first interconnect layer, wherein the second bit line is in parallel with the first bit line;

a second VSS line in the first interconnect layer, wherein the second VSS line is orthogonal to the first VSS line;

a word line in a second interconnect layer over the first interconnect layer;

a third VSS line in the second interconnect layer, wherein the third VSS line is in parallel with the word line; and

a word line strap structure coupled between the gate and the word line.

15. The apparatus of claim 14 , wherein:

the first bit line is orthogonal to the first VSS line; and

the second bit line is orthogonal to the first VSS line.

16. The apparatus of claim 14 , further comprising:

a drain, a source and channel between the drain and the source.

17. The apparatus of claim 16 , wherein:

the drain is connected to the plurality of interconnect structures through a first contact and a second contact formed in the contact layer; and

the gate is connected the plurality of interconnect structures through a third contact formed in the contact layer.

18. The apparatus of claim 17 , wherein:

a height of the gate is equal to a height of the first contact.

19. The apparatus of claim 17 , wherein:

a height of the second contact is equal to a height of the third contact.

20. The apparatus of claim 14 , wherein the word line strap structure comprises:

a gate contact in the contact layer;

a first via in the first interconnect layer:

a first metal line in the first interconnect layer, wherein the first metal line is over the first via; and

a second via in the second interconnect layer, wherein the word line is over the second via.

Continuity (2)
Division 13436452 · Mar 30, 2012
Related Publication 20140231921A1 · Aug 21, 2014