IP Library Granted Patent US 9,306,159
Granted Patent B2
US 9,306,159 · App. 14/266,415 · Granted Apr 5, 2016

Phase change memory stack with treated sidewalls

Inventors: Tsz W. Chan (Boise, ID); Yongjun Jeff Hu (Boise, ID); Swapnil Lengade (Boise, ID); Shu Qin (Boise, ID); Everett Allen McTeer (Eagle, ID)
Assignee: Micron Technology, Inc.
H01L45/06H01L27/2481H01L45/1233H01L45/1253H01L45/141H01L45/165H01L45/1616H01L45/1675
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,306,159
App. No.
14/266,415
Granted
Apr 5, 2016
Kind
B2
Abstract

Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.

Claims (34)

1. A method for fabricating a memory stack, the method comprising:

forming the memory stack out of a plurality of elements;

forming an adhesion species on at least one sidewall of the memory stack, the adhesion species having a gradient structure that results in the adhesion species intermixing with an element of the memory stack, the gradient structure comprising a film of the adhesion species on an outer surface of the at least one sidewall; and

implanting a dielectric material into the film.

2. The method of claim 1 , wherein forming the adhesion species comprises implanting the adhesion species into each sidewall of the memory stack and depositing a film of the adhesion species.

3. The method of claim 1 , wherein forming the adhesion species comprises performing a plasma immersion process and a deposition process.

4. The method of claim 3 , wherein performing the plasma immersion process comprises performing a plasma doping of boron into sidewalls of electrodes of the memory stack.

5. The method of claim 1 , wherein implanting the dielectric material into the film comprises implanting a nitride forming material into the film to form a BN x film sideliner.

6. The method of claim 1 , wherein forming the memory stack out of a plurality of elements comprises:

forming a word line material;

forming a first electrode material on the word line material;

forming a selector device material on the first electrode material;

forming a second electrode material on the selector device material;

forming a phase change material on the second electrode material; and

forming a third electrode material on the phase change material.

7. The method of claim 6 , wherein the first, second, and third electrode materials include carbon.

8. The method of claim 7 , wherein a boron adhesion species terminates unsatisfied atomic bonds of the carbon.

9. The method of claim 6 , wherein forming the word line material comprises forming a material including tungsten.

10. A method for fabricating a memory device comprising:

forming a plurality of memory stacks, each memory stack fabricated by:

forming a first carbon electrode on a word line material;

forming a selector device material on the first carbon electrode;

forming a second carbon electrode on the selector device material;

forming a phase change material on the second carbon electrode;

forming a third carbon electrode on the phase change material;

patterning and etching the selector device material, the first, second, and third carbon electrodes, and the phase change material to form the plurality of memory stacks; and

forming a gradient structured adhesion species on the sidewalls of the memory stack using an implant process and a deposition process, the gradient structure comprising a film of the adhesion species and an implanted adhesion species that intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element; and

forming a liner material on the sidewalls of each memory stack by implanting a dielectric material into the film of the adhesion species.

11. The method of claim 10 , wherein forming the gradient structured adhesion species on the sidewalls comprises:

using a plasma doping process to implant a boron species; and

using a deposition process to form a boron film on the sidewall having the implanted boron species.

12. The method of claim 10 , wherein forming the liner material comprises forming a BN x liner material at least on the second carbon electrode.

13. The method of claim 10 , further comprising forming a dielectric fill material between pairs of the memory stacks.

14. The method of claim 10 , wherein forming the liner material comprises forming the liner material at a temperature of less than 390° C.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2014
From: HU, YONGJUN JEFF; CHAN, TSZ W.; LENGADE, SWAPNIL; MCTEER, EVERETT ALLEN; QIN, SHU
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032823/0180 →
Continuity (1)
Related Publication 20150318468A1 · Nov 5, 2015