Nanowire and planar transistors co-integrated on utbox SOI substrate
Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.
1. A method for making a microelectronic device including the steps as consisting of:
a) making one or several semiconducting bars, designed to form at least one transistor channel or several transistor channels of a first type in a first region of a thin semiconducting layer of a substrate facing an opening in a first mask, said substrate being a semiconductor on insulator type substrate comprising a support layer on which an insulating layer is supported, said thin semiconducting layer being supported on said insulating layer;
b) removing an area from the insulating layer in extension of said opening in said first mask so as to expose said semiconducting bars; and
c) replacing said area removed from said insulating layer by a given dielectric material with a composition and a thickness selected to facilitate capacitive coupling between said support layer and said conducting bars.
2. The method according to claim 1 , in which said insulating layer is based on a first material with a first dielectric constant k 1 , the method also comprising a step consisting of replacing said area of said insulating layer removed in step b) by a given dielectric material with a second dielectric constant k 2 such that k 2 >k 1 .
3. The method according to claim 1 , in which the dielectric material is formed to reach a bottom face of the semiconducting bars located facing the support layer.
4. The method for making a microelectronic device according to claim 1 , also comprising at least one step consisting of:
making at least one isolation trench between said given region and said other region in the thin semiconducting layer.
5. The method for making a microelectronic device according to claim 1 , said insulating layer being based on SiO 2 and being less than 20 nm thick.
6. The method for making a microelectronic device according to claim 1 , in which in step b) another area of the insulating layer, located facing a second region in said thin semiconducting layer in which at least another transistor channel of a second type will be formed, is kept.
7. The method for making a microelectronic device according to claim 1 , also comprising steps to:
remove another area from the insulating layer so as to expose a given region in the support layer,
growth of a semiconducting region on said given region in the support layer, at least one transistor channel will be formed in said semiconducting region.
8. The method for making a microelectronic device according to claim 1 , in which an encasing gate is formed on said bars and around side faces of said bars after step c).
9. The method according to claim 1 , in which said one or several semiconducting bar(s) is (are) formed in step a) by etching the thin semiconducting layer through one or several blocks in a second mask partially covering said opening in said first mask, production of the second mask comprising steps consisting of:
forming one or several sacrificial pads with critical dimension Dc 1 ,
forming one or several masking blocks with critical dimension Dc2<Dc1 in contact with the flanks of said sacrificial pad(s),
removing said sacrificial pad(s).
10. The method for making a microelectronic device according to claim 9 , in which, making said second mask also comprises the following steps after making said first mask and before step a):
deposit a hard mask layer on said first mask and in said opening,
etch the hard mask layer through said blocks with critical dimension Dc 2 so as to form hard mask blocks in extension of said blocks.
11. The method for making a microelectronic device according to claim 9 , in which said blocks are arranged so as to be provided with ends supported on said first mask.
12. A method for making a microelectronic device comprising the steps to:
a) make one or several semiconducting bars that will form at least one transistor channel or several transistor channels of a first type in a first region of a thin semiconducting layer of a substrate facing an opening in a first mask, said substrate being a semiconductor on insulator type substrate comprising a support layer on which an insulating layer is supported, said thin semiconducting layer being supported on said insulating layer, wherein said insulating layer has a first dielectric constant k 1 ;
b) remove an area from said insulating layer in extension of said opening in said first mask so as to expose said semiconducting bars; and
c) replace said area removed from said insulating layer by a given dielectric material with a second dielectric constant k 2 such that k 2 >k 1 .
13. The method for making a microelectronic device according to claim 12 , in which an encasing gate is formed on said bars and around side faces of said bars after step c).