IP Library Granted Patent US 9,015,356
Granted Patent B2
US 9,015,356 · App. 14/268,125 · Granted Apr 21, 2015

Memory controllers, memory systems, solid state drives and methods for processing a number of commands

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Quick Facts
Patent No.
US 9,015,356
App. No.
14/268,125
Granted
Apr 21, 2015
Kind
B2
Abstract

The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Claims (37)

1. A method, comprising:

receiving a number of commands from a host in an order;

re-ordering the number of commands;

combining multiple commands of the number of commands into a single command;

deleting a command of the number of commands that involves a memory location that will be overwritten by a subsequently-executed command of the number of commands without an intervening operation involving the memory location; and

distributing at least one of the number of commands among more than one back end channel.

2. The method of claim 1 , wherein the re-ordering, combining, and deleting occurs only when the more than one back end channel is busy.

3. The method of claim 1 , wherein the re-ordering is in response, at least in part, to the combining multiple commands or the deleting the command.

4. The method of claim 1 , wherein combining multiple commands includes grouping commands of the number of commands involving adjacent memory locations into a single command.

5. The method of claim 1 , wherein combining multiple commands includes grouping commands of the number of commands involving a number of same memory locations into a single command.

6. The method of claim 1 , wherein combining multiple commands includes coalescing commands involving sequential memory locations on a particular memory device into a single command.

7. The method of claim 1 , wherein combining multiple commands includes coalescing commands involving overlapping memory locations on a particular memory device into a single command.

8. The method of claim 1 , further comprising:

determining, for the at least one of the number of commands, a respective logical block address and sector count for each portion of a payload associated with the at least one of the number of commands; and

modifying the at least one of the number of commands distributed to a particular one of the more than one back end channels with the respective logical block address and sector count.

9. The method of claim 1 , wherein distributing at least one of the number of commands includes distributing a fewer number of commands among the plurality of back end channels than the number of commands received from the host.

10. The method of claim 1 , wherein distributing at least one of the number of commands includes distributing a greater number of commands among the plurality of back end channels than the number of commands received from the host.

11. The method of claim 1 , further comprising communicating a result to the host from executing a particular one of the at least one of the number of commands distributed among the plurality of back end channels upon completion, without regard to completion of execution of any other of the at least one of the number of commands distributed among the plurality of back end channels.

12. A method, comprising:

receiving a plurality of host commands to a memory controller from a host in an order;

generating a number of back end commands at least in response to the plurality of host commands; and

distributing the number of back end commands from the memory controller to a plurality of back end channels,

wherein the number of back end commands is different fewer than the plurality of host commands.

13. The method of claim 12 , wherein generating the number of back end commands includes combining multiple host commands into a single back end command.

14. The method of claim 12 , wherein generating the number of back end commands includes splitting one of the plurality of host commands into multiple back end commands.

15. The method of claim 14 , wherein distributing the number of back end commands includes distributing the multiple back end commands at least equal to a number of back end channels.

16. The method of claim 12 , wherein generating the number of back end commands includes not generating a back end command corresponding to a host command that involves a memory location that is to be overwritten by a subsequently host command without an intervening operation involving the memory location.

17. The method of claim 12 , wherein generating the number of back end commands includes at least one of:

modifying at least one of the plurality of host commands; and

deleting at least another one of the plurality of host commands.

18. The method of claim 12 , wherein the number of back end commands is at least equal to a number of back end channels.

19. The method of claim 12 , wherein generating the number of back end commands includes grouping host commands involving adjacent memory locations into a single back end command.

20. A method, comprising:

receiving commands to a memory controller from a host in an order;

combining multiple commands into a single command or deleting a command that involves a memory location determined to be overwritten by a command subsequent in the order without an intervening operation involving the memory location;

re-ordering the commands in response, at least in part, to combining multiple commands or deleting the command; and

distributing the re-ordered commands from the memory controller to more than one back end channel.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2014
From: ASNAASHARI, MEHDI; LIAO, YU-SONG; YANG, JUI-YAO; NEMAZIE, SIAMACK
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032808/0133 →