Synergetic deduplication
Flash memory devices can be implemented with deduplication mechanism through a synergetic deduplication mapping that combines the logical-to-physical address mapping of the flash memory devices with the deduplication mapping. A deduplication algorithm can be implemented in the application layer, which can freely communicate with the flash memory devices and perform computationally expensive operations.
1 . An address mapping table adapted for use with a solid state drive, the address mapping table comprising:
logical addresses of data, wherein the data is configured to be stored in memories of the solid state drive;
physical addresses of the memories,
wherein the address mapping table is configured to map the logical addresses to the physical addresses,
wherein the address mapping table is further configured to map logical addresses of duplicated portions of the data to same physical addresses of memories of the solid state drive.
2 . An address mapping table as in claim 1
wherein the solid state drive comprises a flash memory device.
3 . An address mapping table as in claim 1
wherein the logical addresses are logical page values in the flash memory,
wherein the physical addresses are physical page values in the flash memory.
4 . An address mapping table as in claim 1
wherein the mapping of duplicated portions of data is controlled by a deduplication module.
5 . An address mapping table as in claim 1
wherein the address mapping table comprises an integration of a flash translation mapping and a deduplication mapping.
6 . An address mapping table as in claim 1
wherein the address mapping table is formed based on the data and based on information related to data duplication characteristics.
7 . A solid state drive, the solid state drive comprising:
one or more memory modules;
a controller coupled to the one or more memory modules,
wherein the controller is operable to communicate with a host system for exchanging data between the solid state drive and the host system,
wherein the data is configured to be stored in memories of the one or more memory modules,
wherein the controller is operable to map logical addresses of the data to physical addresses of the memories of the one or more memory modules,
wherein the controller is further operable to map logical addresses of duplicated portions of the data to same physical addresses of the memories of the one or more memory modules.
8 . A solid state drive as in claim 7
wherein the logical addresses are obtained from the host system.
9 . A solid state drive as in claim 7
wherein the mapping of the controller comprises an integration of a flash translation mapping and a deduplication mapping.
10 . A solid state drive as in claim 7
wherein the controller is configured to receive the data and information related to data duplication characteristics to perform the mapping.
11 . A solid state drive as in claim 7
wherein the mapping from logical addresses to physical addresses by the controller is performed by a firmware.
12 . A solid state drive as in claim 7 further comprising
a firmware in a flash translation layer, wherein the firmware is executed by the controller to perform the mapping from logical addresses to physical addresses.
13 . A solid state drive as in claim 7
wherein the mapping from logical addresses to physical addresses is performed with inputs from a deduplication module, wherein the deduplication module is operable to identify duplicated data portions.
14 . A solid state drive as in claim 7 further comprising
a deduplication module, wherein the deduplication module is operable to identify duplicated data portions to assist in the mapping.
15 . A method for forming a solid state drive, the method comprising:
forming one or more memory modules;
forming a controller coupled to the one or more memory modules,
wherein the controller is operable to communicate with a host system for exchanging data between the solid state drive and the host system,
wherein the data is configured to be stored in memories of the one or more memory modules,
wherein the controller is operable to map logical addresses of the data to physical addresses of memories of the one or more memory modules,
wherein the controller is further operable to map logical addresses of duplicated portions of the data to same physical addresses of the memories of the one or more memory modules.
16 . A method as in claim 15 further comprising
installing a firmware to the solid state drive, wherein the firmware is operable to control the mapping from logical addresses of the data to physical addresses.
17 . A method as in claim 15
wherein the mapping of the controller comprises an integration of a flash translation mapping and a deduplication mapping.
18 . A method as in claim 15
wherein the mapping from logical addresses to physical addresses by the controller is performed by a firmware.
19 . A method as in claim 15
wherein the mapping from logical addresses to physical addresses is performed with inputs from a deduplication module from the host system, wherein the deduplication module is operable to identify duplicated data portions.
20 . A method as in claim 15
wherein the mapping from logical addresses to physical addresses is performed by the controller, wherein the controller is configured to perform comparison of data portions to identify duplicated data portions to assist in the mapping.