Wafer, a method for processing a wafer, and a method for processing a carrier

1. A method for processing a wafer, the method comprising:

forming at least one hollow chamber and a support structure within the wafer, the at least one hollow chamber defining a cap region of the wafer located above the at least one hollow chamber and a bottom region of the wafer located below the at least one hollow chamber and an edge region surrounding the cap region of the wafer, wherein a surface area of the cap region is greater than a surface area of the edge region, and wherein the cap region is connected to the bottom region by the support structure;

removing the cap region in one piece from the bottom region and the edge region.

2. The method according to claim 1 ,

wherein removing the cap region comprises rolling up the entire cap region.

3. The method according to claim 1 ,

wherein removing the cap region comprises:

bringing a roller into contact with the cap region, and

subsequently rolling the roller over the wafer, wherein the cap region adheres to the roller.

4. The method according to claim 1 ,

wherein forming the at least one hollow chamber and the support structure within the wafer comprises:

forming at least one opening structure in the wafer and providing a plurality of support regions within the at least one opening structure,

performing an anneal process to form the at least one hollow chamber and the cap region from the at least one opening structure and to form the support structure supporting the cap region from the plurality of support regions.

5. The method according to claim 4 ,

wherein forming the at least one opening structure comprises forming a plurality of openings in the wafer, the plurality of openings surrounding the plurality of support regions and extending from a surface of the wafer into the wafer.

6. The method according to claim 4 ,

wherein the wafer comprises silicon and wherein the anneal process is performed at a temperature of at least about 900° C.

7. The method according to claim 1 ,

wherein forming the at least one hollow chamber and the support structure within the wafer comprises:

forming at least one porous structure in the wafer and providing a plurality of support regions within the porous structure,

performing an anneal process to form the at least one hollow chamber and the cap region from the at least one porous structure and to form the support structure supporting the cap region from the plurality of support regions.

8. The method according to claim 7 ,

wherein forming the at least one porous structure comprises forming a plurality of porous regions in the wafer, the plurality of porous regions surrounding the plurality of support regions.

9. The method according to claim 7 ,

wherein the wafer comprises silicon and wherein the anneal process is performed at a temperature of at least about 900° C.

10. The method according to claim 1 ,

wherein forming the support structure comprises forming a plurality of support structure elements being arranged spaced apart from each other, the plurality of support structure elements extending within the at least one hollow chamber and supporting the cap region.

11. The method according to claim 1 ,

wherein forming the at least one hollow chamber and the support structure comprises forming a plurality of hollow chambers being arranged spaced apart from each other such that a plurality of support structure elements are provided between the plurality of hollow chambers, the plurality of support structure elements supporting the cap region.

12. The method according to claim 1 ,

wherein forming the support structure comprises forming a plurality of support structure elements having a pitch in the range from about 10 μm to about 100 μm.

13. The method according to claim 7 ,

wherein forming the support structure comprises forming a plurality support structure elements having a cross-sectional area of less than about 100 μm 2 .

14. The method according to claim 1 ,

wherein forming the support structure comprises forming more than 100 support structure elements supporting a cap region area of about 1 mm 2 .

15. The method according to claim 1 ,

wherein removing the cap region in one piece from the bottom region and the edge region comprises:

forming a trench structure extending from the surface of the cap region to the at least one hollow chamber, the trench structure laterally surrounding the cap region completely, and

removing the cap region in one piece from the bottom region thereby cracking the support structure.

16. The method according to claim 1 ,

wherein removing the cap region in one piece from the bottom region and the edge region comprises:

forming a trench structure extending from the surface of the cap region to the at least one hollow chamber, the trench structure laterally surrounding the cap region partially such that a connection structure remains connecting the cap region and the edge region; and

removing the cap region in one piece from the bottom region and the edge region thereby cracking the support structure and the connection structure.

17. The method according to claim 1 , further comprising:

processing a plurality of processing regions of the cap region, wherein at least a first processing region of the plurality of processing regions and a second processing region of the plurality of processing regions differ from each other in at least one of size or shape.

18. The method according to claim 1 , further comprising:

forming a first electronic circuit structure with a first active area in the cap region, and

forming a second electronic circuit structure with a second active area in the cap region, wherein the first active area and the second active area differ from each other in at least one of size or shape.

19. A method for processing a carrier, the method comprising:

forming a hollow chamber within the carrier, the hollow chamber being covered by a cap region, wherein the cap region is supported via a plurality of support structure elements extending within the hollow chamber, wherein the plurality of support structure elements are spaced apart from each other with a first pitch;

processing a plurality of processing areas in the cap region, wherein the plurality of processing areas are spaced apart from each other with a second pitch, wherein the first pitch of the plurality of support structure elements is less than the second pitch of the plurality of processing areas.

20. A wafer comprising:

a hollow chamber within the wafer and a support structure extending within the hollow chamber, the hollow chamber being covered by a cap region, wherein the cap region is supported by the support structure, and wherein the hollow chamber undermines more than 80% of a processing surface of the wafer.