Memory device refresh commands on the fly
On the fly switching from one memory device refresh rate to another is provided. Control logic associated with the memory device detects a condition to switch from a currently-applied refresh rate to a different refresh rate. In response to the condition, the refresh rate is dynamically switched. The switching does not require a change of a mode register. Thus, a refresh rate for the memory device can be dynamically changed on the fly.
1. An apparatus comprising:
logic to couple to memory resources, the logic to dynamically select between two sets of refresh cycle time (tRFC) and refresh interval time (tREF) to refresh storage elements of the memory resources wherein the two sets include different refresh cycle times and different refresh interval times;
at least one register to specify the following modes of operation:
i) a normal refresh mode;
ii) a first on-the-fly mode of operation having a first set of refresh cycle time and refresh interval time;
iii) a second on-the-fly mode of operation having a second set of refresh cycle time and refresh interval time;
wherein a control entity is able to dynamically select amongst the i), ii) and iii) modes of operation to cause the manner of operating the memory resources to be dynamically changed without having to change a value that specifies a particular refresh cycle time or refresh interval time.
2. The apparatus of claim 1 , wherein a first refresh interval time in a first of the sets is one half a second refresh interval time in a second of the sets.
3. The apparatus of claim 1 , wherein a first refresh interval time in a first of the sets is 1.0 times refresh cycle time and a second refresh interval in a second of the sets is 4.0 times refresh cycle time.
4. The apparatus of claim 1 , wherein a state of a bank group (BG) pin is used to identify selection of one of the sets.
5. A method comprising:
a) setting information in register space to:
not select a normal refresh mode;
select an on-the-fly mode;
choose one on-the-fly mode setting from amongst first and second on-the-fly mode settings, the first and second on-the-fly mode settings specifying different sets of refresh cycle time (tRFC) and average refresh interval time (tREF), the choosing not requiring changing of a value that specifies a particular refresh cycle time or refresh interval time;
b) dynamically triggering selection between two sets of refresh cycle time (tRFC) and average refresh interval time (tREF) to refresh the storage elements of memory resources wherein the two sets include different refresh cycle times and different refresh interval times.
6. The method of claim 5 , wherein a first refresh interval time in a first of the sets is one half a second refresh interval time in a second of the sets.
7. The method of claim 5 , wherein a first refresh interval in a first of the sets is 1.0 times refresh cycle time and a second refresh interval in a second of the sets is 4.0 times refresh cycle time.
8. The method of claim 5 , wherein a state of a bank group (BG) pin is used to identify which one of the sets is selected.
9. A system comprising:
a processor;
memory resources coupled to the processor, the memory resources to store data;
a memory controller coupled to the memory resources, the memory controller including electronic circuitry to dynamically select between two sets of refresh cycle time (tRFC) and refresh interval time (tREF) to refresh storage elements of the memory resources wherein the two sets include different refresh cycle times and different refresh interval times; and,
at least one register to specify the following modes of operation:
i) a normal refresh mode;
ii) a first on-the-fly mode of operation having a first set of refresh cycle time and refresh interval time specified in the at least one register;
iii) a second on-the-fly mode of operation having a second set of refresh cycle time and refresh interval time specified in the at least one register;
wherein a control entity is to dynamically select amongst the i), ii) and iii) modes of operation to cause the manner of operating the memory resources to be dynamically changed without having to change a value that specifies a particular refresh cycle time or refresh interval time.
10. The system of claim 9 , wherein a first refresh interval time in a first of the sets is one half a second refresh interval time in a second of the sets.
11. The system of claim 9 , wherein a first refresh interval in a first of the sets is 1.0 times refresh cycle time and a second refresh interval in a second of the sets is 4.0 times refresh cycle time.
12. The system of claim 9 , wherein a state of a bank group (BG) pin is used to identify which one of the sets is selected.
13. The system of claim 9 , wherein the memory controller comprises the at least one register.