IP Library Granted Patent US 9,202,771
Granted Patent B2
US 9,202,771 · App. 14/271,390 · Granted Dec 1, 2015

Semiconductor chip structure

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Quick Facts
Patent No.
US 9,202,771
App. No.
14/271,390
Granted
Dec 1, 2015
Kind
B2
Abstract

A semiconductor chip structure including a semiconductor chip having a pair of electrodes is disclosed. The electrodes have different conductivity types for electrical connection, respectively. A thermoelectric cooling material layer is disposed within each of the pair of electrodes, respectively.

Claims (79)

1. A semiconductor chip structure, comprising:

a semiconductor chip having a pair of electrodes, wherein the electrodes have different conductivity types for electrical connection; and

a thermoelectric cooling material layer disposed within each of the pair of electrodes;

wherein an operating current I opt applied to each of the thermoelectric cooling material layers is in a range of

α

T

c

-

(

α

T

c

)

2

-

2

k

ρ

Δ

T

ρ

<

I

opt

×

L

/

A

<

α

T

c

+

(

α

T

c

)

2

-

2

k

ρ

Δ

T

ρ

,

 and wherein L represents a length of the thermoelectric cooling material layer, A represents a contact area of the thermoelectric cooling material layer, T c represents a cold-end temperature, T h represents a hot-end temperature, α represents a seeback coefficient, ρ represents a resistivity of the thermoelectric cooling material layer, k represents a thermal conductivity of the thermoelectric cooling material layer, and ΔT represents a temperature difference between T c and T h .

2. The semiconductor chip structure as claimed in claim 1 , wherein the pair of electrodes comprises a P-type electrode and an N-type electrode.

3. The semiconductor chip structure as claimed in claim 2 , wherein the P-type electrode and the N-type electrode comprise a wire layer.

4. The semiconductor chip structure as claimed in claim 3 , wherein the P-type electrode and the N-type electrode further comprise an adhesive layer.

5. The semiconductor chip structure as claimed in claim 4 , wherein the adhesive layer comprises a single layer or multiple layers.

6. The semiconductor chip structure as claimed in claim 4 , wherein each of the thermoelectric cooling material layers is interposed between the wire layer and the adhesive layer.

7. The semiconductor chip structure as claimed in claim 6 , wherein the wire layer and the adhesive layer have different temperatures.

8. The semiconductor chip structure as claimed in claim 1 , further comprising a power unit electrically connected to the P-type electrode and the N-type electrode to construct a same electrical circuit.

9. The semiconductor chip structure as claimed in claim 1 , wherein the semiconductor chip is a light-emitting diode chip or a high-voltage flip chip.

10. The semiconductor chip structure as claimed in claim 1 , wherein the thermoelectric cooling material layers comprise BiSb, Bi 2 Te 3 , PbTe, CeFe 4-x Co x Sb 12 or SiGe.

Assignments (2)
MERGER Recorded Mar 27, 2026
From: LEXTAR ELECTRONICS CORPORATION
To: ENNOSTAR CORPORATION
Reel/Frame 075286/0822 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2014
From: CHEN, YI-JYUN
To: LEXTAR ELECTRONICS CORPORATION
Reel/Frame 032854/0184 →