IP Library Granted Patent US 9,171,619
Granted Patent B2
US 9,171,619 · App. 14/275,727 · Granted Oct 27, 2015

Method and apparatus for configuring write performance for electrically writable memory devices

Inventors: Gerald Barkley (Oregon, WI); Poorna Kale (Folsom, CA)
Assignee: Micron Technology, Inc.
G11C14/009G11C13/0069G11C16/10G11C16/102G11C16/20G11C13/0004G11C13/0038G11C16/30
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Quick Facts
Patent No.
US 9,171,619
App. No.
14/275,727
Granted
Oct 27, 2015
Kind
B2
Abstract

Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory is associated with a configuration register to indicate a write speed setting for at least one write operation to the nonvolatile memory. A circuit may supply current to achieve an indicated write speed setting for the at least one write operation to the nonvolatile memory.

Claims (33)

1. A system comprising:

a circuit configured to supply current for write operations to a nonvolatile memory; and

a processing element configured to:

determine a write speed based on power consumption of the system; and

control the circuit to provide an amount of current to perform a write operation at the write speed,

wherein the write speed is dynamic, wherein a maximum amount of available current supplied for some write operations is different than a maximum amount of available current supplied for other write operations.

2. The system of claim 1 , wherein the processing element is configured to increase the write speed of the write operations to the nonvolatile memory by controlling the circuit to increase the current supplied for the write operations.

3. The system of claim 1 , wherein the processing element is configured to determine an amount of available current to supply for a write operation, the amount of available current based on current usage of the system.

4. The system of claim 1 , wherein the processing element is configured to change the write speed of the write operations to the nonvolatile memory by controlling a power management unit to change the current supplied for the write operation, the power management unit configured to determine power consumption of the system.

5. The system of claim 1 , wherein the processing element is configured to determine power consumption of the system based on a number of idle electronic components of the system.

6. The system of claim 1 , wherein the processing element is configured to control the circuit to provide a fixed speed for a write operation.

7. The system of claim 1 , wherein a performance speed of the write operations is based on the amount of current supplied to the nonvolatile memory.

8. The system of claim 1 , wherein the nonvolatile memory is configured to store information comprising at least one of data or program code.

9. The system of claim 1 , where the nonvolatile memory comprises at least one of a Phase-Change Memory (“PCM”), flash memory, and/or Electrically Erasable Programmable Read-Only Memory (“EEPROM”).

10. The system of claim 1 , wherein the write speed is user-selectable.

11. A method, comprising:

determining a write speed for write operations to a nonvolatile memory based on current consumption of a system comprising the nonvolatile memory; and

supplying an amount of current to perform a write operation to the nonvolatile memory at a write speed,

wherein the write speed is dynamic, wherein a maximum amount of available current supplied for some write operations is different than a maximum amount of available current supplied for other write operations.

12. The method of claim 11 , further comprising changing the write speed of the write operations to the nonvolatile memory by changing the amount of current supplied for the write operation, the write speed of the write operations to the nonvolatile memory based on the amount of current supplied for the write operations.

13. The method of claim 12 , wherein changing the write speed comprises increasing the write speed by increasing the amount of current supplied for the write operations.

14. The method of claim 11 , further comprising determining an amount of available current to supply for a write operation, the amount of available current based on a number of idle electronic components of the system comprising the nonvolatile memory.

15. The method of claim 11 , further comprising supplying an amount of current to perform a write operation to the nonvolatile memory at a fixed speed.

16. The method of claim 11 , further comprising selecting the write speed.

17. A system comprising:

a circuit configured to supply current for write operations to a nonvolatile memory; and

a processing element configured to:

determine a write speed based on a number of idle electronic components of the system; and

control the circuit to provide an amount of current to perform a write operation at the write speed,

wherein the write speed is dynamic, wherein a maximum amount of available current supplied for some write operations is different than a maximum amount of available current supplied for other write operations.

18. The system of claim 17 , wherein the processing element is configured to determine an amount of available current to supply for a write operation, the amount of available current based on current usage of the system.

19. The system of claim 17 , wherein the processing element is configured to change the write speed of the write operations to the nonvolatile memory by controlling the circuit to change the current supplied for the write operations.

20. The system of claim 19 , wherein the processing element is configured to increase the write speed of the write operations to the nonvolatile memory by controlling the circuit to increase the current supplied for the write operations.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Continuation 12337573 · Dec 17, 2008
Related Publication 20140337563A1 · Nov 13, 2014