IP Library › Granted Patent US 9,875,795
Granted Patent B2
US 9,875,795 · App. 14/277,282 · Granted Jan 23, 2018

Memory architecture and cell design employing two access transistors

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Quick Facts
Patent No.
US 9,875,795
App. No.
14/277,282
Granted
Jan 23, 2018
Kind
B2
Abstract

Some embodiments include an improved memory array architecture and memory cell design. In one of such embodiments, a memory cell may comprise a memory element to store a logic state and two access transistors coupled to the memory element to access the logic state of the memory element. Other embodiments are described.

Claims (55)

1. A memory cell comprising:

a memory element to store a logic state, wherein the memory element comprises a first phase change material that is isolated from a second phase change material of an adjacent memory element, such that the first phase change material and the second phase change material are not connected to each other by a third phase change material, and wherein the memory element further includes a first terminal that is coupled to a bit line; and

first and second access transistors coupled to the memory element, the first and second access transistors to access the logic state of the memory element, the first access transistor including a channel terminal sharing a first diffusion region with a first additional access transistor of a first additional memory cell, and the second access transistor including a channel terminal sharing a second diffusion region with a second additional access transistor of a second additional memory cell, wherein,

the first access transistor is coupled to a first word line,

the second access transistor is coupled to a second word line,

the first diffusion region is coupled to a first conductive line,

the second diffusion region is coupled to a second conductive line,

a physical structure of each of the first and second conductive lines has a length parallel with a physical structure of each of the first and second word lines,

the first and the second access transistors are independently selectable by the first and second word lines, and

the first and second access transistors are coupled to the memory element via a second terminal.

2. The memory cell of claim 1 , wherein the first and second access transistors share a third diffusion region.

3. The memory cell of claim 1 , wherein the first and second access transistors share a third diffusion region, and the third diffusion region is coupled to a bit line.

4. The memory cell of claim 1 , wherein the memory element is coupled to a decoder via the first terminal.

5. The memory cell of claim 1 , wherein the first and second diffusion regions are located in a substrate, and the memory element is located outside the substrate.

6. The memory cell of claim 1 , wherein each of the first and second access transistors includes a gate located between the memory element and a substrate.

7. The memory cell of claim 1 , wherein the memory element includes a combination of germanium, antimony, and telluride.

8. A memory cell comprising:

a memory element to store a logic state, wherein the memory element comprises a first phase change material that is isolated from a second phase change material of an adjacent memory element, such that the first phase change material and the second phase change material are not connected to each other by a third phase change material, and wherein the memory element further includes a first terminal that is coupled to a bit line; and

first and second access transistors coupled to the memory element, the first and second access transistors to access the logic state of the memory element, the first access transistor including a channel terminal sharing a first diffusion region with a first additional access transistor of a first additional memory cell, and the second access transistor including a channel terminal sharing a second diffusion region with a second additional access transistor of a second additional memory cell, wherein the first and second access transistors share a third diffusion region, wherein,

the first and second access transistors are coupled to the memory element via a second terminal,

the first access transistor is coupled to a first word line,

the second access transistor is coupled to a second word line,

the first diffusion region is coupled to a first conductive line,

the second diffusion region is coupled to a second conductive line, and

a physical structure of each of the first and second conductive lines has a length parallel with a physical structure of each of the first and second word lines.

9. The memory cell of claim 8 , further comprising a reference driver to place a reference potential on the first and second conductive lines.

10. The memory cell of claim 9 , wherein the bit line is perpendicular to the first and second word lines.

11. The memory cell of claim 10 , wherein a dimension of the second terminal less than the dimension of the phase change material.

12. A memory cell comprising:

a memory element to store a logic state, wherein the memory element comprises material that is isolated from a material of an adjacent memory element, and wherein the memory element further includes a first terminal that is coupled to a bit line; and

first and second access transistors coupled to the memory element, the first and second access transistors to access the logic state of the memory element, the first access transistor including a channel terminal sharing a first diffusion region with a first additional access transistor of a first additional memory cell, and the second access transistor including a channel terminal sharing a second diffusion region with a second additional access transistor of a second additional memory cell, wherein the first and the second access transistors are independently selectable by two word lines, wherein the first and second access transistors are coupled to the memory element via a second terminal, wherein,

the memory element includes one of a fuse, an antifuse, and a capacitor,

the first access transistor is coupled to a first word line,

the second access transistor is coupled to a second word line,

the first diffusion region is coupled to a first conductive line,

the second diffusion region is coupled to a second conductive line, and

a physical structure of each of the first and second conductive lines has a length parallel with a physical structure of each of the first and second word lines.

13. A memory cell comprising:

a memory element to store a logic state, wherein the memory element comprises material that is isolated from a material of an adjacent memory element, and wherein the memory element further includes a first terminal that is coupled to a bit line; and

first and second access transistors coupled to the memory element, the first and second access transistors to access the logic state of the memory element, the first access transistor including a channel terminal sharing a first diffusion region with a first additional access transistor of a first additional memory cell, and the second access transistor including a channel terminal sharing a second diffusion region with a second additional access transistor of a second additional memory cell, wherein the first and the second access transistors are independently selectable by two word lines, wherein the first and second access transistors are coupled to the memory element via a second terminal, wherein,

the memory element includes a resistive random access memory element,

the first access transistor is coupled to a first word line,

the second access transistor is coupled to a second word line,

the first diffusion region is coupled to a first conductive line,

the second diffusion region is coupled to a second conductive line, and

a physical structure of each of the first and second conductive lines has a length parallel with a physical structure of each of the first and second word lines.

14. A memory cell comprising:

a memory element to store a logic state, wherein the memory element comprises material that is isolated from a material of an adjacent memory element, and wherein the memory element further includes a first terminal that is coupled to a bit line; and

first and second access transistors coupled to the memory element, the first and second access transistors to access the logic state of the memory element, the first access transistor including a channel terminal sharing a first diffusion region with a first additional access transistor of a first additional memory cell, and the second access transistor including a channel terminal sharing a second diffusion region with a second additional access transistor of a second additional memory cell, wherein the first and the second access transistors are independently selectable by two word lines, wherein the first and second access transistors are coupled to the memory element via a second terminal, wherein,

the memory element includes a magnetoresistive random access memory element,

the first access transistor is coupled to a first word line,

the second access transistor is coupled to a second word line,

the first diffusion region is coupled to a first conductive line,

the second diffusion region is coupled to a second conductive line, and

a physical structure of each of the first and second conductive lines has a length parallel with a physical structure of each of the first and second word lines.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2016
From: MICRON TECHNOLOGY, INC
To: OVONYX MEMORY TECHNOLOGY, LLC
Reel/Frame 039974/0496 →