IP Library Granted Patent US 10,110,375
Granted Patent B2
US 10,110,375 · App. 14/278,318 · Granted Oct 23, 2018

Cryptographic device and secret key protection method

Inventor: Ching-Wen Ma (Hsinchu County, TW)
Assignee: MSTAR SEMICONDUCTOR, INC.
H04L9/0643H04L9/003H04L2209/046H04L2209/08H04L2209/16
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Quick Facts
Patent No.
US 10,110,375
App. No.
14/278,318
Granted
Oct 23, 2018
Kind
B2
Abstract

A cryptographic device and a secret key protection method are provided. The cryptographic device protects a secret key of the cryptographic device when processing a message. The cryptographic device includes: a secret key protection circuit, configured to generate an anti-crack protection signal according to the message and the secret key by a hash calculation circuit; and a cryptographic processor, configured to process the message and the secret key according to the anti-crack protection signal to generate an encrypted message.

Claims (44)

1. A cryptographic device as applied to a communication device, that protects a secret key of the cryptographic device when processing a message from a side channel attack, comprising:

a secret key protection circuit, configured to generate an anti-crack protection signal by performing a hash operation on the message and the secret key by a hash calculation circuit; and

a cryptographic circuit, configured to encrypt the message into an encrypted message using the secret key at a time determined by the anti-crack protection signal to impede side channel attacks that use differential power analysis.

2. The cryptographic device according to claim 1 , wherein the hash calculation circuit generates a hash value according to the message and the secret key, and the secret key protection circuit further comprises:

a shift register processing circuit, configured to generate the anti-crack protection signal according to the hash value; and

a buffer, configured to receive the anti-crack protection signal.

3. The cryptographic device according to claim 2 , wherein the shift register processing circuit comprises:

a plurality of register units, comprising:

an input register unit, configured to receive the hash value; and

an output register unit, configured to output the anti-crack protection signal; and

a logic calculation unit, configured to generate a logic calculation value according to the hash value, and to generate the anti-crack protection signal by utilizing the logic calculation value.

4. The cryptographic device according to claim 2 , wherein the secret key protection circuit further comprises:

a dummy circuit, configured to obfuscate the energy consumption caused by the shift register processing circuit.

5. The cryptographic device according to claim 1 , wherein the hash calculation circuit comprises:

a first hash calculation unit, configured to generate a part of a hash value according to the message; and

a second hash calculation unit, configured to generate one other part of the hash value according to the secret key.

6. The cryptographic device according to claim 1 , wherein the hash calculation circuit comprises:

a first hash calculation unit, configured to generate an initial hash value according to one of the message and the secret key; and

a second hash calculation unit, configured to generate a hash value according to one other of the message and the secret key and the initial hash value.

7. The cryptographic device according to claim 1 , further comprising:

a control circuit, configured to control the cryptographic processor and/or the secret key protection circuit according to a detection signal and a predetermined condition, wherein the detection signal indicates whether the message is present, and the predetermined condition corresponds to one of a predetermined time and a speed of generating the anti-crack protection signal.

8. The cryptographic device according to claim 7 , wherein the control circuit controls the cryptographic processor according to the detection signal and the predetermined condition to obtain the anti-crack protection signal from the secret key protection circuit, or to control the secret key protection circuit to provide the anti-crack protection signal to the cryptographic processor.

9. A secret key protection method, applied to a cryptographic device applied to a communication device, for protecting a secret key of the cryptographic device when the cryptographic device processes a message from a side channel attack, the secret key protection method comprising:

generating a hash value by performing a hash operation on the message and the secret key;

generating an anti-crack protection signal according to the hash value; and

encrypting the message into an encrypted message using the secret key at a time determined by the anti-crack protection signal to impede side channel attacks that use differential power analysis.

10. The secret key protection method according to claim 9 , wherein the step of processing the message and the secret key according to the anti-crack protection signal to generate the anti-crack protection message and the anti-crack protection secret key, respectively, comprises:

performing a masking operation on the message and the secret key according to the anti-crack protection signal to generate the anti-crack protection message and the anti-crack protection secret key, respectively.

11. The secret key protection method according to claim 9 , wherein the step of generating the anti-crack protection signal according to the hash value comprises:

performing a shift register process according to the hash value to generate the anti-crack protection signal.

12. The secret key protection method according to claim 11 , wherein the step of performing the shift register process according to the hash value to generate the anti-crack protection signal comprises:

receiving the hash value;

performing a logic calculation process according to the hash value to generate a logic calculation value; and

generating the anti-crack protection signal according to the logic calculation value.

13. The secret key protection method according to claim 11 , wherein the step of performing the shift register process according to the hash value to generate the anti-crack protection signal further comprises:

obfuscating energy consumption caused by the shift register process by utilizing a dummy circuit.

14. The secret key protection method according to claim 9 , wherein the step of generating the hash value according to the message and the secret key comprises:

generating a part of the hash value according to the message; and

generating one other part of the hash value according to the secret key.

15. The secret key protection method according to claim 9 , wherein the step of generating the hash value according to the message and the secret key comprises:

generating an initial hash value according to one of the message and the secret key; and

generating the hash value according to one other of the message and the secret key and the initial hash value.

16. The secret key protection method according to claim 9 , further comprising:

controlling starting time points of the step of generating the anti-crack protection signal and the step of generating the encrypted signal according to a detection signal and a predetermined condition, wherein the detection signal indicates whether the message is present, and the predetermined condition corresponds to one of a predetermined time and a speed of generating the anti-crack protection signal.

Assignments (2)
MERGER Recorded Jun 12, 2020
From: MSTAR SEMICONDUCTOR, INC.
To: MEDIATEK INC.
Reel/Frame 052931/0468 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2014
From: MA, CHING-WEN
To: MSTAR SEMICONDUCTOR, INC.
Reel/Frame 032902/0650 →
Priority Claims (1)
TW 102118148 A · May 23, 2013 · national
Continuity (1)
Related Publication 20160119136A1 · Apr 28, 2016
Cited By (2)
US 12,353,570 US 12,562,884