IP Library › Patent Application 14278901
Patent Application
App. No. 14/278,901

TECHNIQUES FOR THE CANCELLATION OF CHIP SCALE PACKAGING PARASITIC LOSSES

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Quick Facts
Patent No.
US None
App. No.
14/278,901
Abstract

The present invention generally relates to techniques and structures that cancel or mitigate RF coupling from the RF circuit to the silicon die. To cancel or mitigate the RF coupling, a conductive coating may be formed over the RF-MEMS device. The conductive coating may be coupled to the die. Alternatively, the conductive coating may be coupled to the die through the RF-MEMS by having a through silicon via. Another manner for cancelling or mitigating RF coupling is to have no conductive traces located on the front side of the PCB.

Claims (15)

1 . A CSP RF-MEMS device, comprising:

a printed circuit board having a plurality of conductive traces disposed on a side thereof;

a solder mask layer disposed over at least one conductive trace;

a die having sidewalls, a backside, and a frontside;

pads coupled to the frontside of the die;

conductive bumps coupled to the pads and the conductive traces; and

a conductive shield disposed over the sidewalls and backside of the die.

2 . The CSP RF-MEMS device of claim 1 , wherein the conductive shield is coupled to at least one trace of the plurality of conductive traces.

3 . The CSP RF-MEMS device of claim 1 , wherein die has a filled through silicon via extending from the backside to the frontside and wherein the conductive shield is coupled to the filled through silicon via.

4 . A CSP RF-MEMS device, comprising:

a printed circuit board having one or more first conductive traces disposed on a side thereof, one or more second conductive traces disposed on the same side as the one or more first conductive traces, and one or more third conductive traces embedded within the printed circuit board, the one or more second conductive traces are coupled to the one or more third conductive traces through conductive filled vias;

a solder mask layer disposed over one or more first conductive traces;

a die having sidewalls, a backside, and a frontside;

pads coupled to the frontside of the die; and

conductive bumps coupled to the pads and the one or more second conductive traces.

Assignments (2)
PLAN OF DISSOLUTION OF CAVENDISH KINETICS INC. Recorded Feb 10, 2022
From: CAVENDISH KINETICS INC.
To: QORVO US, INC.
Reel/Frame 059113/0181 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 6, 2014
From: GADDI, ROBERTO; VAN KAMPEN, ROBERTUS PETRUS; YOST, DENNIS J; CASTILLOU, PAUL ALBERT; SHINGAL, ATUL PRAKASH
To: CAVENDISH KINETICS, INC.
Reel/Frame 033477/0223 →