IP Library Granted Patent US 9,018,654
Granted Patent B2
US 9,018,654 · App. 14/281,385 · Granted Apr 28, 2015

Semiconductor light emitting device and light emitting apparatus

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Quick Facts
Patent No.
US 9,018,654
App. No.
14/281,385
Granted
Apr 28, 2015
Kind
B2
Abstract

According to one embodiment, a semiconductor light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer, a light emitting layer, a p-side electrode and an n-side electrode. The p-type semiconductor layer includes a nitride semiconductor and has a first major surface. The n-type semiconductor layer includes a nitride semiconductor and has a second major surface. The light emitting layer is provided between the n-type semiconductor layer and the p-type semiconductor layer. The p-side electrode contacts a part of the p-type semiconductor layer on the first major surface. The n-side electrode contacts a part of the n-type semiconductor layer on the second major surface. The n-side electrode is provided outside and around the p-side electrode in a plan view along a direction from the p-type semiconductor layer to the n-type semiconductor layer.

Claims (33)

1. A semiconductor light emitting device comprising:

a p-type semiconductor layer including a nitride semiconductor and having a first major surface;

an n-type semiconductor layer including a nitride semiconductor and having a second major surface;

a light emitting layer provided between the n-type semiconductor layer and the p-type semiconductor layer, the first major surface being on a side of the p-type semiconductor layer opposite to the light emitting layer, the second major surface being on a side of the n-type semiconductor layer opposite to the light emitting layer;

a p-side electrode contacting a first region of the p-type semiconductor layer on the first major surface;

an n-side electrode contacting a second region of the n-type semiconductor layer on the second major surface; and

a high resistance region provided on the first major surface of the p-type semiconductor layer, the high resistance region having a part outside the first region in a plan view along a direction from the p-type semiconductor layer to the n-type semiconductor layer, and an electrical resistance between the high resistance region and the p-type semiconductor layer being higher than an electrical resistance between the p-side electrode and the p-type semiconductor layer in the first region,

the n-side electrode being provided outside and around the first region in the plan view.

2. The device according to claim 1 , wherein

the first region of the p-side electrode contacting the p-type semiconductor layer includes Ni, and

a part of the high resistance region contacting the p-type semiconductor layer includes Ti.

3. The device according to claim 1 , wherein

the p-side electrode is covered with the high resistance region, and

the n-side electrode is overlapped with a part of the high resistance region in the plan view.

4. The device according to claim 1 , wherein

the n-side electrode is apart from the first region in the plan view,

a gap between the n-side electrode and the first region in the plan view is larger than a thickness of the n-type semiconductor layer.

5. The device according to claim 1 , wherein

the n-side electrode surrounds a whole outer edge of the first region in the plan view.

6. The device according to claim 1 , wherein

the n-side electrode surrounds a whole outer edge of the first region continuously in the plan view.

7. The device according to claim 1 , wherein

the n-side electrode includes at least one selected from the group of Ti, Al, Rh, In, Ni, Pt and Au.

8. The device according to claim 1 , further comprising

a wavelength conversion layer configured to absorb a first light emitted from the light emitting layer to emit a second light having a wavelength different from a wavelength of the first light.

9. The device according to claim 1 , wherein

the n-side electrode is apart from the first region in the plan view,

a gap between the n-side electrode and the first region in the plan view is larger than a sum of a thickness of the n-type semiconductor layer, a thickness of the light emitting layer, and a thickness of the p-type semiconductor layer.

10. The device according to claim 1 , wherein

a gap between the n-side electrode and the first region in the plan view is equal to or larger than five micrometers.

11. The device according to claim 1 , wherein

the first major surface is a mounting surface, and

the second major surface is a light extraction surface.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2020
From: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
To: SEOUL SEMICONDUCTOR CO., LTD.
Reel/Frame 052316/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2020
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA ELECTRONIC DEVICES AND STORAGE CORPORATION
Reel/Frame 051691/0442 →