Semiconductor device and method of manufacturing the same

1. A semiconductor device, comprising:

a first member including first and second transistors on a front surface side of a first semiconductor substrate, the first transistor being a memory selection transistor, the second transistor being other than a memory selection transistor; and

a second member including an insulating layer in which are embedded first and second resistance change devices, a conductive layer, and first and second connection layer portions, the first connection layer portion connecting the first resistance change device with the first transistor, the second connection layer portion connecting the second resistance change device with the second transistor, the first and second resistance change devices being commonly connected to the conductive layer, the insulating layer of the second member being bonded to the semiconductor substrate at a back surface of the first member.

2. The semiconductor device according to claim 1 , wherein each resistance change device is a spin injection magnetization reversal type memory device that includes a record layer, a tunnel barrier layer, and a reference layer in this order starting from a side close to the connection layer portion.

3. The semiconductor device according to claim 1 , wherein the first member includes a back surface contact electrode extending between the selection transistor and the connection layer portion, the back surface contact electrode penetrating through the first substrate.

4. The semiconductor device according to claim 1 , wherein the second transistor is part of a logic circuit.

5. A semiconductor device comprising:

first and second members that are adjacent to each other, the first member including a semiconductor substrate, the substrate having oppositely facing first and second sides, the second member including an insulating layer having oppositely facing first and second sides, the first side of the second member adjacent the second side of the substrate, the first and second members having a memory device section and a peripheral device section along a first direction, the first and second members being adjacent along a second direction orthogonal to the first direction;

a plurality of transistors at the first side of the substrate, the plurality of transistors including a pair of selection transistors and a peripheral transistor, the selection transistors being adjacent along the first direction, the selection transistors being within the memory device section, the peripheral transistor being within the peripheral device section, gates of the selection transistors being word lines;

a source line commonly connected to both selection transistors;

a connection layer on the first side of the insulating layer and extending along the first direction, the connection layer separated into isolated portions, each connection layer portion corresponding to a respective transistor;

a bit line in the insulating layer and extending in the first direction;

a resistance change layer in the insulating layer and extending along the first direction, the resistance change layer separated into isolated portions, each resistance change layer portion corresponding to a respective connection layer portion, each resistance change layer portion connected to both its respective connection layer portion and the bit line; and

a plurality of electrodes, each extending in a second direction from the first side of the substrate to the second side of the substrate, each electrode interconnecting a respective connection layer portion and a respective transistor.