Mixed-sized pillars that are probeable and routable
View Patent ↗An integrated circuit with probeable and routable interfaces is disclosed. The integrated circuit includes multiple micro-pillars that are attached to the surface of the integrated circuit, and multiple macro-pillars also attached to the surface of the integrated circuit. The micro-pillars provide an electrical interface to the integrated circuit during regular operation. The macro-pillars provide an electrical interface to the integrated circuit both during regular operation and during testing of the integrated circuit.
1. An integrated circuit operable in either a test mode or a normal operation mode, the integrated circuit comprising:
a plurality of micro-pillars attached to a surface of the integrated circuit, the micro-pillars comprising copper pillars capped by solder;
a plurality of macro-pillars also attached to the surface of the integrated circuit, the macro-pillars comprising copper pillars capped by solder, each macro-pillar covering a larger area than each micro-pillar, wherein the macro-pillars and the micro-pillars have substantially similar heights; and
the macro-pillars and the micro-pillars providing an electrical interface to the integrated circuit, responsive to the integrated circuit being in normal operation mode; and
the macro-pillars providing an electrical interface to the integrated circuit, responsive to the integrated circuit being in test mode.
2. The integrated circuit of claim 1 , wherein the copper pillars of the micro-pillars and the copper pillars of the macro-pillars are formed by electroplating.
3. The integrated circuit of claim 1 , wherein the copper pillars of the micro-pillars are formed independently of the copper pillars of the macro-pillars.
4. The integrated circuit of claim 1 , further comprising:
a switch, one of the macro-pillars coupled to the switch, the switch configured to couple the macro-pillar to a first circuit of the integrated circuit responsive to the integrated circuit being in test mode and to couple the macro-pillar to a second circuit of the integrated circuit responsive to the integrated circuit being in normal operation mode.
5. The integrated circuit of claim 1 , further comprising:
a selector having two inputs, one of the macro-pillars coupled to one of the inputs and one of the micro-pillars coupled to the other of the inputs, the selector configured to couple the macro-pillar to a first circuit of the integrated circuit responsive to the integrated circuit being in test mode and to couple the micro-pillar to the first circuit of the integrated circuit responsive to the integrated circuit being in normal operation mode.
6. The integrated circuit of claim 1 wherein the micro-pillar has a diameter smaller than 45 μm.
7. The integrated circuit of claim 1 wherein the macro-pillar has a diameter greater than 90 μm.
8. The integrated circuit of claim 1 , wherein the macro-pillars are probeable using a vertical probe card.
9. The integrated circuit of claim 1 , wherein the plurality of macro-pillars and the plurality of micro-pillars are randomly arranged across the surface of the integrated circuit.
10. The integrated circuit of claim 1 , wherein the plurality of macro-pillars are arranged around a perimeter of the surface of the integrated circuit.
11. The integrated circuit of claim 1 , wherein the plurality of macro-pillars are arranged in a central region of the surface of the integrated circuit.
12. The integrated circuit of claim 1 , wherein the plurality macro-pillars are periodically arranged across the surface of the integrated circuit, and at least one or more micro-pillars from the plurality of micro-pillars are arranged in between two macro-pillars of the plurality of macro-pillars.
13. The integrated circuit of claim 1 , wherein at least one of the plurality of macro-pillars is for supplying power to the integrated circuit.
14. A composite integrated circuit structure comprising:
an integrated circuit having a first surface, with a plurality of micro-pillars and a plurality of macro-pillars attached to the first surface, the macro-pillars switchably connectable to testing circuitry on the integrated circuit; and
a device having a second surface, the micro-pillars and macro-pillars contacting the second surface, the micro-pillars and macro-pillars configured to provide an electrical interface between the integrated circuit and the device.
15. The composite integrated circuit structure of claim 14 , wherein the device is a silicon interposer, and wherein the silicon interposer comprises a first plurality of contact pads and a second plurality of contact pads, each contact pad of the second plurality of contact pads covering a larger area than each contact pad from the first plurality of contact pads.
16. The composite integrated circuit structure of claim 14 , wherein the device is configured to have a third surface, the third surface configured to provide an electrical interface between the device and a printed circuit board.
17. The composite integrated circuit structure of claim 14 , wherein the plurality of micro-pillars and the plurality of macro-pillars of the integrated circuit are used for flip chip bonding the integrated circuit to the device.
18. A method for manufacturing an integrated circuit, the method comprising:
defining a first set of regions with a first dimension;
depositing metal on the defined first set of regions to form a first set of pillars with the first dimension;
after depositing metal on the defined first set of regions:
defining a second set of regions with a second dimension, the second dimension different than the first dimension, and
depositing metal on the defined second set of regions to form a second set of pillars with the second dimension; and
depositing metal on the first set of pillars and the second set of pillars.