Memory controller for strobe-based memory systems
An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.
1. An integrated circuit (IC) memory controller comprising:
a receiver to receive a strobe signal and provide an internal strobe signal;
an adjustable delay circuit that delays an enable signal to generate a delayed enable signal;
a gate circuit to generate a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal; and
a sample circuit to sample data using the gated strobe signal.
2. The IC memory controller according to claim 1 , wherein:
the enable signal is received from a circuit operating in a first clock domain; and
the strobe signal is received from a memory device operating in a second clock domain.
3. The IC memory controller according to claim 2 , wherein:
the first clock domain is associated with a first master clock of a first frequency; and
the second clock domain is associated with a second master clock of a second frequency different than the first frequency.
4. The IC memory controller according to claim 1 , wherein:
the delay applied to the enable signal to generate the delayed enable signal is based on a phase relationship between the enable signal and the strobe signal.
5. The IC memory controller according to claim 4 , further comprising:
storage to store a value corresponding to the phase relationship between the enable signal and the strobe signal.
6. The IC memory controller according to claim 5 , wherein:
the value is determined and loaded into the storage during a calibration mode of operation.
7. The IC memory controller according to claim 5 , further comprising:
error detection circuitry to determine the value during the calibration mode.
8. The IC memory controller according to claim 1 , wherein:
the adjustable delay circuit controls the delay so as to position a transitioning edge of the delayed enable signal to coincide in time with the valid region of the internal strobe signal.
9. The IC memory controller according to claim 8 , wherein:
the gate circuit includes logic to generate the gated strobe signal in response to receiving the transitioning edge of the delayed enable signal and the internal strobe signal.
10. A method of operation in an IC memory controller, the method comprising:
receiving a strobe signal;
providing an internal strobe signal based on the received strobe signal;
delaying an enable signal to generate a delayed enable signal;
gating the strobe signal to generate a gated strobe signal, the gating including using the delayed enable signal to mask transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal; and
sampling data using the gated strobe signal.
11. The method according to claim 10 , wherein:
receiving the enable signal comprises receiving the enable signal from a circuit operating in a first clock domain; and
receiving the strobe signal comprises receiving the strobe signal from a memory device operating in a second clock domain.
12. The method according to claim 10 , wherein:
delaying the enable signal to generate the delayed enable signal includes applying a delay based on a phase relationship between the enable signal and the strobe signal.
13. The method according to claim 12 , further comprising:
storing a value representing the delay, the value corresponding to the phase relationship between the enable signal and the strobe signal.
14. The method according to claim 11 , further comprising:
determining the value during a calibration mode of operation; and
loading the value into storage during the calibration mode of operation.
15. The method according to claim 14 , further comprising:
controlling the delay so as to position a transitioning edge of the delayed enable signal to coincide in time with the valid region of the internal strobe signal.
16. A Field Programmable Gate Array (FPGA) device comprising:
a receiver to receive a strobe signal and provide an internal strobe signal;
an adjustable delay circuit that delays an enable signal to generate a delayed enable signal;
a gate circuit to generate a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal; and
a sample circuit to sample data using the gated strobe signal.
17. The FPGA according to claim 16 , wherein:
the FPGA device is embodied as a dynamic random access (DRAM) memory controller, and the sampled data comprises read data.
18. The FPGA according to claim 16 , wherein:
the delay applied to the enable signal to generate the delayed enable signal is based on a phase relationship between the enable signal and the strobe signal.
19. The FPGA according to claim 16 , further comprising:
storage to store a value corresponding to the phase relationship between the enable signal and the strobe signal.
20. The FPGA according to claim 16 , wherein:
the adjustable delay circuit controls the delay so as to position a transitioning edge of the delayed enable signal to coincide in time with the valid region of the internal strobe signal.