IP Library Patent Application 14285730
Patent Application
App. No. 14/285,730

APPARATUS FOR PROCESSING A SEMICONDUCTOR WORKPIECE

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Quick Facts
Patent No.
US None
App. No.
14/285,730
Abstract

An apparatus for processing a semiconductor workpiece includes a first chamber having a first plasma production source and a first gas supply for introducing a supply of gas into the first chamber, a second chamber having a second plasma production source and a second gas supply for introducing a supply of gas into the second chamber, a workpiece support positioned in the second chamber, and a plurality of gas flow pathway defining elements for defining a gas flow pathway in the vicinity of the workpiece when positioned on the workpiece support. The gas flow path defining elements include at least one wafer edge region protection element for protecting the edge of the wafer and/or a region outwardly circumjacent to the edge of the wafer, and at least one auxiliary element spaced apart from the wafer edge region protection element to define the gas flow pathway.

Claims (28)

1 . An apparatus for processing a semiconductor workpiece including:

a first chamber having a first plasma production source and a first gas supply for introducing a supply of gas into the first chamber;

a second chamber having a second plasma production source and a second gas supply for introducing a supply of gas into the second chamber, the second gas supply being independently controllable of the first gas supply;

a workpiece support positioned in the second chamber; and

a plurality of gas flow pathway defining elements for defining a gas flow pathway in the vicinity of the workpiece when positioned on the workpiece support, wherein the gas flow path defining elements include at least one wafer edge region protection element for protecting the edge of the wafer and/or a region outwardly circumjacent to the edge of the wafer, and at least one auxiliary element spaced apart from the wafer edge region protection element to define the gas flow pathway.

2 . An apparatus according to claim 1 in which the wafer edge region protection device element is an annular wafer edge protection device.

3 . An apparatus according to claim 1 in which the at least one auxiliary element includes one or more baffles.

4 . An apparatus according to claim 3 at which the at least one auxiliary element is an annular baffle.

5 . An apparatus according to claim 1 in which the auxiliary element is positioned over an inner portion of the wafer edge region protection element.

6 . An apparatus according to claim 1 in which the auxiliary element is positioned over an outer part of the wafer edge region protection element.

7 . An apparatus according to claim 1 in which the auxiliary element extends radially inward of the wall of the second chamber.

8 . An apparatus according to claim 1 in which the auxiliary element extends downwardly from the wall of the second chamber.

9 . An apparatus according to claim 1 in which the auxiliary element is spaced apart from the wafer edge region protection element to define a gap of between 2 and 80 mm, preferably between 5 and 50 mm, most preferably between 15 and 25 mm.

10 . An apparatus according to claim 1 in which the gas flow pathway extends radially outwards from the workpiece when positioned on the workpiece support.

11 . An apparatus according to claim 1 in which the workpiece, when positioned on the workpiece support, is supported by a carrier, and the wafer edge region protection element protects the carrier.

12 . An apparatus according to claim 11 in which the carrier is of the tape and frame kind, and the wafer edge protection element protects the tape and/or the frame.

13 . An apparatus according to claim 1 in which the first plasma production source includes an element for coupling energy into the first chamber to maintain a plasma induced in the first chamber, and the second plasma production source includes an element for coupling energy into the second chamber to maintain a plasma induced in the second chamber, wherein the element of the first plasma production source is spaced apart from the element of the second plasma production source so as to decouple the plasma induced in the first chamber from the plasma induced in the second chamber.

14 . An apparatus according to claim 13 in which the first chamber meets the second chamber at an interface having an associated level, and at least one of the elements of the first plasma production source and the elements of the second plasma production source is spaced apart from said level.

15 . An apparatus for processing a semiconductor workpiece including;

a first chamber having a first plasma production source including an element for coupling energy into the first chamber to maintain a plasma induced in the first chamber, and a first gas supply for introducing a supply of gas into the first chamber;

a second chamber having a second plasma production source including an element for coupling energy into the first chamber to maintain a plasma induced in the second chamber and a second gas supply for introducing a supply of gas into the second chamber, the second gas supply being independently controllable of the first gas supply; and

a workpiece support positioned in the second chamber;

wherein the element of the first plasma production source is spaced apart from the element of the second plasma production source so as to decouple the plasma induced in the first chamber from the plasma induced in the second chamber.

16 . An apparatus for processing a semiconductor workpiece including:

a chamber having a wall;

a workpiece support positioned in the chamber;

at least one plasma production source; and

a plurality of gas flow pathway defining elements for defining a gas flow pathway in the vicinity of the workpiece when positioned on the workpiece support, wherein the gas flow pathway defining elements include at least one wafer edge region protection element for protecting the edge of the wafer and/or a region outwardly circumjacent to the edge of the wafer, and at least one auxiliary element spaced apart from the wafer edge region protection element to define the gas flow pathway.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Jul 5, 2016
From: JPMORGAN CHASE BANK, N.A.
To: SPTS TECHNOLOGIES LIMITED
Reel/Frame 039257/0026 →
SECURITY INTEREST Recorded Apr 2, 2015
From: SPTS TECHNOLOGIES LIMITED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 035364/0295 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2014
From: ANSELL, OLIVER; KIERNAN, BRIAN; JEFFERY, TOBY; VARVARA, MAXIME
To: SPTS TECHNOLOGIES LIMITED
Reel/Frame 033474/0342 →