Neutralization of parasitic capacitance using MOS device
View Patent ↗An apparatus comprises an amplifier comprising at least one metal oxide semiconductor (MOS) transistor having a parasitic gate-to-drain capacitance, and at least one MOS neutralization device having a neutralization capacitance configured to compensate for the parasitic gate-to-drain capacitance of the at least one MOS transistor.
1. An apparatus, comprising:
a first positive channel metal oxide semiconductor (PMOS) transistor having a source connected to a first node, a drain connected to a second node, and a gate connected to a third node;
a second PMOS transistor having a source connected to the first node, a drain connected to a fourth node, and a gate connected to a fifth node;
a first negative channel metal oxide semiconductor (NMOS) transistor having a source connected to a sixth node, a drain connected to the second node, and a gate connected to a seventh node;
a second NMOS transistor having a source connected to the sixth node, a drain connected to the fourth node, and a gate connected to an eighth node;
a first metal oxide semiconductor (MOS) differential neutralization device connected between the third node and the fourth node;
a second MOS differential neutralization device connected between the fifth node and the second node;
a third MOS differential neutralization device connected between the seventh node and the fourth node; and
a fourth MOS differential neutralization device connected between the eighth node and the second node, wherein the first through fourth MOS differential neutralization devices comprise PMOS capacitors.
2. The apparatus of claim 1 , wherein each of the PMOS capacitors has a bulk connected to a power supply voltage.
3. The apparatus of claim 1 , wherein the first and second MOS differential neutralization devices together comprise either NMOS or PMOS capacitors, and the third and fourth MOS differential neutralization devices together comprise either NMOS or PMOS capacitors.
4. The apparatus of claim 1 , wherein the first node is connected to a supply voltage and the sixth node is connected to ground.
5. The apparatus of claim 1 , wherein at least one of the first through fourth differential neutralization devices comprises an oxide layer formed in conjunction with an oxide layer of at least one of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, the second NMOS transistor.
6. The apparatus of claim 1 , wherein the first and second PMOS transistors and the first and second NMOS transistors form an H-bridge.
7. The apparatus of claim 1 , wherein the first and second PMOS transistors and the first and second NMOS transistors form a differential amplifier.
8. An apparatus, comprising:
a differential amplifier comprising first and second metal oxide semiconductor (MOS) transistors arranged in parallel, the first MOS transistor comprising a gate that receives a positive input signal among a differential pair of input signals, a drain that outputs a negative output signal among a differential pair of output signals, and a source connected to a reference voltage, and the second MOS transistor comprising a gate that receives a negative input signal among the differential pair of input signals, a drain that outputs a positive output signal among the differential pair of output signals, and a source connected to the reference voltage;
a first MOS differential neutralization device connected between the gate of the first MOS transistor and the drain of the second MOS transistor; and
a second MOS differential neutralization device connected between the gate of the second MOS transistor and the drain of the first MOS transistor, wherein the first and second MOS differential neutralization devices each comprise a positive channel metal oxide semiconductor (PMOS) transistor.
9. The apparatus of claim 8 , wherein each of the first and second MOS devices comprises an NMOS transistor or a PMOS transistor.
10. The apparatus of claim 8 , wherein the differential amplifier further comprises additional MOS transistors arranged with the first and second MOS transistors in an H-bridge configuration.
11. An apparatus, comprising:
a first positive channel metal oxide semiconductor (PMOS) transistor having a source connected to a first node, a drain connected to a second node, and a gate connected to a third node;
a second PMOS transistor having a source connected to the first node, a drain connected to a fourth node, and a gate connected to a fifth node;
a first negative channel metal oxide semiconductor (NMOS) transistor having a source connected to a sixth node, a drain connected to the second node, and a gate connected to a seventh node;
a second NMOS transistor having a source connected to the sixth node, a drain connected to the fourth node, and a gate connected to an eighth node;
a first metal oxide semiconductor (MOS) differential neutralization device connected between the third node and the fourth node;
a second MOS differential neutralization device connected between the fifth node and the second node;
a third MOS differential neutralization device connected between the seventh node and the fourth node; and
a fourth MOS differential neutralization device connected between the eighth node and the second node, wherein the first through fourth MOS differential neutralization devices comprise NMOS capacitors.
12. The apparatus of claim 11 , wherein each of the NMOS capacitors has a bulk connected to ground.
13. The apparatus of claim 11 , wherein the first and second PMOS transistors and the first and second NMOS transistors form an H-bridge.
14. The apparatus of claim 11 , wherein the first and second PMOS transistors and the first and second NMOS transistors form a differential amplifier.
15. The apparatus of claim 11 , wherein the first node is connected to a supply voltage and the sixth node is connected to ground.
16. The apparatus of claim 11 , wherein at least one of the first through fourth differential neutralization devices comprises an oxide layer formed in conjunction with an oxide layer of at least one of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, the second NMOS transistor.
17. An apparatus, comprising:
a first positive channel metal oxide semiconductor (PMOS) transistor having a source connected to a first node, a drain connected to a second node, and a gate connected to a third node;
a second PMOS transistor having a source connected to the first node, a drain connected to a fourth node, and a gate connected to a fifth node;
a first negative channel metal oxide semiconductor (NMOS) transistor having a source connected to a sixth node, a drain connected to the second node, and a gate connected to a seventh node;
a second NMOS transistor having a source connected to the sixth node, a drain connected to the fourth node, and a gate connected to an eighth node;
a first metal oxide semiconductor (MOS) differential neutralization device connected between the third node and the fourth node;
a second MOS differential neutralization device connected between the fifth node and the second node;
a third MOS differential neutralization device connected between the seventh node and the fourth node; and
a fourth MOS differential neutralization device connected between the eighth node and the second node, wherein the first through fourth MOS differential neutralization devices comprise NMOS capacitors, wherein the first and second MOS differential neutralization devices together comprise either NMOS or PMOS capacitors, and the third and fourth MOS differential neutralization devices together comprise either NMOS or PMOS capacitors.
18. The apparatus of claim 17 , wherein the first and second PMOS transistors and the first and second NMOS transistors form an H-bridge.
19. The apparatus of claim 17 , wherein the first and second PMOS transistors and the first and second NMOS transistors form a differential amplifier.
20. The apparatus of claim 17 , wherein the first node is connected to a supply voltage and the sixth node is connected to ground.
21. The apparatus of claim 17 , wherein at least one of the first through fourth differential neutralization devices comprises an oxide layer formed in conjunction with an oxide layer of at least one of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, the second NMOS transistor.
22. An apparatus, comprising:
a first positive channel metal oxide semiconductor (PMOS) transistor having a source connected to a first node, a drain connected to a second node, and a gate connected to a third node;
a second PMOS transistor having a source connected to the first node, a drain connected to a fourth node, and a gate connected to a fifth node;
a first negative channel metal oxide semiconductor (NMOS) transistor having a source connected to a sixth node, a drain connected to the second node, and a gate connected to a seventh node;
a second NMOS transistor having a source connected to the sixth node, a drain connected to the fourth node, and a gate connected to an eighth node;
a first metal oxide semiconductor (MOS) differential neutralization device connected between the third node and the fourth node;
a second MOS differential neutralization device connected between the fifth node and the second node;
a third MOS differential neutralization device connected between the seventh node and the fourth node; and
a fourth MOS differential neutralization device connected between the eighth node and the second node, wherein each of the first through fourth MOS differential neutralization devices is a native MOS device.
23. An apparatus, comprising:
a differential amplifier comprising first and second metal oxide semiconductor (MOS) transistors arranged in parallel, the first MOS transistor comprising a gate that receives a positive input signal among a differential pair of input signals, a drain that outputs a negative output signal among a differential pair of output signals, and a source connected to a reference voltage, and the second MOS transistor comprising a gate that receives a negative input signal among the differential pair of input signals, a drain that outputs a positive output signal among the differential pair of output signals, and a source connected to the reference voltage;
a first MOS differential neutralization device connected between the gate of the first MOS transistor and the drain of the second MOS transistor; and
a second MOS differential neutralization device connected between the gate of the second MOS transistor and the drain of the first MOS transistor, wherein the first and second MOS differential neutralization devices is a native MOS device.