Electrostatic discharge devices and methods of manufacture

1. A method, comprising:

forming a plurality of fin structures and a mesa structure from semiconductor material;

forming an epitaxial material with doped regions on the mesa structure;

forming gate material over at least the plurality of fin structures;

planarizing at least the gate material such that the gate material and the epitaxial material are of a same height; and

forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.

2. The method of claim 1 , wherein the epitaxial material is a crystalline material grown on an exposed surface of the mesa structure.

3. The method of claim 1 , wherein the epitaxial material and the mesa structure form an electrostatic discharge device of a same height as a gate structure.

4. The method of claim 1 , wherein the doped regions of the epitaxial material are formed by separate ion implantation processes which reach into the mesa structure.

5. The method of claim 4 , wherein the gate material is formed over the mesa structure and the planarizing comprises chemical mechanical polishing of the epitaxial material and the gate material to a same height.

6. The method of claim 5 , wherein the fin structures and the mesa structure are formed from a silicon on insulator (SOI) material in a same etching process.

7. The method of claim 6 , wherein the fin structures and mesa structure are separated by an insulating material.

8. The method of claim 7 , further comprising forming nitride sidewalls on sidewalls of the epitaxial material.

9. A method comprising:

forming a plurality of fin structures and a mesa structure from silicon on insulator material;

forming a blocking material on the fin structures and the mesa structure;

removing the blocking material from the mesa structure, exposing the silicon on insulator material of the mesa structure;

growing an epitaxial material on the exposed silicon on insulator material of the mesa structure;

implanting impurities into the epitaxial material with respective ion implantation processes for positive and negative impurities;

forming gate material over at least the plurality of fin structures and the epitaxial material;

planarizing the gate material and the epitaxial material to a same height; and

forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.

10. The method of claim 9 , wherein the implanting impurities into the epitaxial material reaches into the mesa structure.

11. The method of claim 9 , wherein the mesa structure and the fin structures are separated from one another by an oxide material.

12. The method of claim 9 , wherein the gate material includes a high-k dielectric material and metal materials formed on the high-k dielectric material.

13. The method of claim 9 , wherein the mesa structure and the fin structures have substantially a same height.

14. The method of claim 9 , wherein the planarizing is a chemical mechanical polishing.

15. The method of claim 9 , wherein the epitaxial material is a crystalline material.

16. The method of claim 15 , wherein the mesa structure is precleaned to expose the silicon on insulator material, prior to the growing of the crystalline material.

17. The method of claim 16 , wherein the epitaxial material and the mesa structure form an electrostatic discharge device.

18. The method of claim 17 , further comprising forming nitride sidewalls on sidewalls of the epitaxial material.