Method for fabricating an electronic device with anti-oxidation layers
An electronic device includes a semiconductor memory circuit. The semiconductor memory circuit includes a plurality of first conductive lines which includes an anti-oxidation layer on both sides of each first conductive line, an inter-layer dielectric layer suitable for gap-filling a space between the first conductive lines, a material layer formed over the first conductive lines and the inter-layer dielectric layer and including oxygen vacancies, and a plurality of second conductive lines formed over the material layer to intersect with the first conductive lines. A first portion of the material layer where the first conductive lines and the second conductive lines overlap each other has a lower oxygen content than a second portion of the material layer where the inter-layer dielectric layer and the second conductive lines overlap each other.
1. A method for fabricating an electronic device, the method comprising:
forming a stacked structure over a substrate, the stacked structure including a first inter-layer dielectric layer, a first anti-oxidation layer, a horizontal electrode, and a second anti-oxidation layer, which are vertically stacked;
forming a plurality of first openings that expose the substrate by penetrating through the stacked structure;
forming a material layer including oxygen vacancies on sidewalls of the first openings;
forming a plurality of vertical electrodes to fill the first openings; and
causing a portion in the material layer to react with oxygen ions migrated from the first inter-layer dielectric layer.
2. The method according to claim 1 , wherein the material layer includes a transition metal oxide.
3. The method according to claim 1 , wherein the portion in the material layer includes at least some of the oxygen vacancies.
4. The method according to claim 3 , wherein the first anti-oxidation layer and the second anti-oxidation layer include a nitride.
5. The method according to claim 4 , wherein the causing comprises performing a thermal treatment on a structure resulting from the forming of the plurality of vertical electrodes.
6. The method according to claim 1 , further comprising:
forming an isolation layer to penetrate through the stacked structure between two adjacent vertical electrodes, wherein the two adjacent vertical electrodes and the isolation layer are spaced apart from one another.
7. The method according to claim 6 , further comprising:
forming a second inter-layer dielectric layer over the isolation layer and the stacked structure divided by the plurality of vertical electrodes;
forming a plurality of contacts over the plurality of vertical electrodes to be coupled with the vertical electrodes; and
forming a plurality of conductive lines over the second inter-layer dielectric layer and the contacts.