Semiconductor package having EMI shielding and method of fabricating the same
View Patent ↗A semiconductor package includes a dielectric layer in which a chip is embedded, interconnection parts disposed on a first surface of the dielectric layer, through connectors each of which penetrates a portion of the dielectric layer over the chip to electrically couple the chip to a corresponding one of the interconnection parts, a shielding plate covering a second surface of the dielectric layer that is opposite to the first surface, and a shielding encapsulation part connected to one of the interconnection parts and covering sidewalls of the dielectric layer. The shielding encapsulation part includes a portion contacting the shielding plate.
1. A semiconductor package, comprising:
a chip embedded in a dielectric layer;
interconnection parts disposed on a first surface of the dielectric layer;
through connectors each of which penetrates a portion of the dielectric layer over the chip, each of the through connectors electrically coupling the chip to one of the interconnection parts;
a shielding plate covering a second surface of the dielectric layer that is opposite to the first surface; and
a shielding encapsulation part connected to one of the interconnection parts, covering sidewalls of the dielectric layer, and including a portion that contacts the shielding plate,
wherein the interconnection parts include:
a ground interconnection part to which the shielding encapsulation part is connected; and
one or more signal interconnection parts being separated from the ground interconnection part and the shielding encapsulation part,
wherein the ground interconnection part includes:
a first ground contact portion electrically coupled to one of the through connectors;
a second ground contact portion corresponding to a portion of the shielding encapsulation part; and
a ground connection portion electrically coupling the first ground contact portion to the second ground contact portion, and
wherein the signal interconnection parts, the first and second ground contact portions, the ground connection portion, and the shielding encapsulation part are included in different regions of a single layer.
2. The semiconductor package of claim 1 , wherein the shielding encapsulation part covers part of the first surface of the dielectric layer between the signal interconnection parts.
3. The semiconductor package of claim 1 , wherein the shielding encapsulation part covers edge portions of the first surface of the dielectric layer.
4. The semiconductor package of claim 1 , wherein a portion of the shielding encapsulation part contacts sidewalls of the shielding plate.
5. The semiconductor package of claim 1 , wherein a portion of the shielding encapsulation part contacts top surfaces of edge portions of the shielding plate.
6. The semiconductor package of claim 1 , wherein the shielding encapsulation part covers entire surfaces of sidewalls of the dielectric layer.
7. The semiconductor package of claim 1 , wherein the through connectors include bumps penetrating the portion of the dielectric layer over the chip.
8. The semiconductor package of claim 1 , further comprising one or more vertically stacked chips embedded in the dielectric layer and disposed between the chip and the shielding plate.
9. The semiconductor package of claim 8 , wherein the chip and the stacked chips are vertically stacked to have a step structure.
10. The semiconductor package of claim 8 , wherein the chip and the stacked chips are stacked and are vertically aligned with each other.
11. The semiconductor package of claim 8 , further comprising inter-chip connectors electrically coupling the chip to the stacked chips.
12. The semiconductor package of claim 11 , wherein the inter-chip connectors include any of wires and through electrodes.