Semiconductor device
View Patent ↗A semiconductor device including a gate insulating film; a gate electrode; a source region of a first conductivity; a drain region of the first conductivity type; a drift region of the first conductivity type formed between the channel region and the drain region; a first semiconductor region of a second conductivity type that encloses the source region, the drift region and the drain region, and includes the channel region; and a first shield wiring that encloses a portion of the source region in a plan view in conjunction with the gate electrode, the portion being not covered by the gate electrode, and is connected to the first semiconductor region, or that covers the portion and is connected to the first semiconductor region and the source region.
1. A semiconductor device comprising:
a semiconductor substrate that includes a channel region;
a gate insulating film formed on the channel region of the semiconductor substrate;
a gate electrode formed on the gate insulating film;
a source region of a first conductivity type formed in the semiconductor substrate;
a drain region of the first conductivity type formed in the semiconductor substrate;
a drift region of the first conductivity type formed between the channel region and the drain region, the drift region having an impurity concentration lower than an impurity concentration of the drain region;
a first semiconductor region of a second conductivity type opposite to the first conductivity type that encloses the source region, the drift region and the drain region, and includes the channel region in a plan view;
a first shield wiring formed above the semiconductor substrate and electrically connected to the first semiconductor region; and
a second shield wiring formed above the first shield wiring and electrically connected to the first shield wiring,
wherein the source region includes a first portion that is not covered by the gate electrode in a plan view;
the first portion is enclosed by the first shield wiring together with the gate electrode in a plan view, and
the drift region is enclosed by an inner edge of the second shield wiring in a plan view, the inner edge being located above the first shield wiring.
2. The semiconductor device according to claim 1 , further comprising:
a second semiconductor region of the first conductivity type that encloses the first semiconductor region in a plan view.
3. The semiconductor device according to claim 1 ,
wherein the first shield wiring is not disposed between the gate electrode and the drain region in a plan view.
4. The semiconductor device according to claim 1 ,
wherein the second shield wiring is not disposed between the gate electrode and the drain region in a plan view.
5. The semiconductor device according to claim 1 , further comprising:
a wiring formed above the second shield wiring.
6. The semiconductor device according to claim 1 ,
wherein a distance between the drain region and the channel region in a direction from the source region to the drain region is longer than a length of the channel region in the direction.
7. The semiconductor device according to claim 1 , further comprising
a first contact plug, that is connected to the first shield wiring, formed on the first semiconductor region,
wherein the first semiconductor region includes a first part located under the first contact plug and a second part located under the gate electrode, and
the first part and the second part is located continuously.
8. The semiconductor device according to claim 1 , wherein
the inner edge of the second shield wiring is located in the first semiconductor region in a plan view.
9. The semiconductor device according to claim 1 , wherein
the first shield wiring is located in a first interlayer insulating film; and
whole of the second shield wiring is located on the first interlayer insulating film.
10. A semiconductor device comprising:
a semiconductor substrate that includes a channel region;
a gate insulating film formed on the channel region of the semiconductor substrate;
a gate electrode formed on the gate insulating film;
a source region of a first conductivity type formed in the semiconductor substrate;
a drain region of the first conductivity type formed in the semiconductor substrate;
a drift region of the first conductivity type formed between the channel region and the drain region, the drift region having an impurity concentration lower than an impurity concentration of the drain region;
a first semiconductor region of a second conductivity type opposite to the first conductivity type that encloses the source region, the drift region and the drain region, and includes the channel region in a plan view;
a first shield wiring formed above the semiconductor substrate and electrically connected to the first semiconductor region and the source region; and
a second shield wiring formed above the first shield wiring and electrically connected to the first shield wiring,
wherein the source region is covered by the first shield wiring in a plan view, and
the drift region is enclosed by an inner edge of the second shield wiring in a plan view, the inner edge being located above the first shield wiring.
11. The semiconductor device according to claim 10 , further comprising:
a second semiconductor region of the first conductivity type that encloses the first semiconductor region in a plan view.
12. The semiconductor device according to claim 10 ,
wherein the first shield wiring is not disposed between the gate electrode and the drain region in a plan view.
13. The semiconductor device according to claim 10 ,
wherein the second shield wiring is not disposed between the gate electrode and the drain region in a plan view.
14. The semiconductor device according to claim 10 , further comprising:
a wiring formed above the second shield wiring.
15. The semiconductor device according to claim 10 ,
wherein a distance between the drain region and the channel region in a direction from the source region to the drain region is longer than a length of the channel region in the direction.
16. The semiconductor device according to claim 10 , further comprising
a first contact plug, that is connected to the first shield wiring, formed on the first semiconductor region,
wherein the first semiconductor region includes a first part located under the first contact plug and a second part located under the gate electrode, and
the first part and the second part is located continuously.
17. The semiconductor device according to claim 16 ; wherein
material of the first contact plug is different from material of the first shield wiring.
18. The semiconductor device according to claim 10 , wherein
the inner edge of the second shield wiring is located in the first semiconductor region in a plan view.
19. The semiconductor device according to claim 10 , wherein
the first shield wiring is located in a first interlayer insulating film; and
whole of the second shield wiring is located on the first interlayer insulating film.