High density single-transistor antifuse memory cell

1. A memory cell comprising:

a thin gate insulator;

a bulk region of a first conductivity type in contact with a first side of the thin gate insulator;

a polysilicon gate electrode of the first conductivity type in contact with a second side of the thin gate insulator; and

a source region of a second conductivity type in contact with the bulk region at a junction, wherein the second conductivity type is different from the first conductivity type, further wherein the junction forms a diode for the memory cell and the junction is laterally spaced from the thin gate insulator and does not directly underlie the thin gate insulator;

wherein the bulk region is in an active layer of a semiconductor-on-insulator structure comprising a buried insulator and a substrate layer; and

wherein the thin gate insulator is blown upon application of a programming voltage addressed to the memory cell across the polysilicon gate electrode and the source region.

2. The memory cell of claim 1 , wherein:

the thin gate insulator is less than 50 angstroms thick;

the programming voltage to blow the thin gate insulator exceeds 10 volts; and

the source region is located in the active layer of the semiconductor-on-insulator structure.

3. The memory cell of claim 1 , wherein:

the junction is at least 0.3 microns from the thin gate insulator.

4. The memory cell of claim 1 , further comprising:

a layer of polysilicon comprising the polysilicon gate electrode of the first conductivity type and a region of undoped polysilicon;

wherein the region of undoped polysilicon is in contact with the second side of the thin gate insulator and a masking layer; and

wherein the junction is also in contact with the masking layer.

5. The memory cell of claim 1 , wherein:

the bulk region is physically remote from every region of the second conductivity type in the semiconductor-on-insulator structure besides the source region.

6. The memory cell of claim 1 , wherein the junction is laterally spaced from the thin gate insulator by at least 0.3 micrometers.

7. The memory cell of claim 1 , wherein the junction is laterally spaced from the thin gate insulator by at least 0.5 micrometers.

8. A memory cell comprising:

a thin gate insulator;

a bulk region in an active layer of a semiconductor on insulator wafer, wherein the bulk region is of a first conductivity type and contacts a first side of the thin gate insulator;

a gate electrode that contacts a second side of the thin gate insulator; and

a source region of a second conductivity type in the active layer of the semiconductor on insulator wafer, wherein the source region contacts the bulk region at a junction, wherein the junction forms a diode for the memory cell and the junction is laterally spaced from the thin gate insulator and does not directly underlie the thin gate insulator; and

wherein the gate electrode and the source region are operatively coupled to a programming voltage source that addresses the memory cell by blowing the thin gate insulator.

9. The memory cell of claim 8 , wherein:

the thin gate insulator is less than 50 angstroms thick; and

the programming voltage source provides a programming voltage in excess of 10 volts to the polysilicon gate electrode and the source region.

10. The memory cell of claim 8 , wherein:

the junction is at least 0.3 microns from the thin gate insulator.

11. The memory cell of claim 8 , wherein:

the bulk region is not in contact with a drain region.

12. The memory cell of claim 8 , wherein:

the bulk region has a first conductivity type;

the gate electrode is polysilicon of the first conductivity type; and

the source region has a second conductivity type.

13. The memory cell of claim 8 , further comprising:

a layer of polysilicon comprising the gate electrode of the first conductivity type and a region of undoped polysilicon;

wherein the region of undoped polysilicon is in contact with the second side of the thin gate insulator and a masking layer; and

wherein the junction is also in contact with the masking layer.

14. An apparatus comprising:

an active layer having a first region located between one side of a thin gate insulator and a buried insulator of a semiconductor on insulator wafer;

a gate electrode in contact with a second side of the thin gate insulator;

a contact coupled to the active layer;

a program control line that causes a programming voltage to be applied across the gate electrode and the contact;

wherein the thin gate insulator breaks to form a current branch from the gate electrode through the first region to the contact when the programming voltage is applied; and

wherein a junction on the current branch forms a diode, and the junction is laterally spaced from the thin gate insulator and does not directly underlie the thin gate insulator;

the apparatus further comprising: a second region of the active layer having an opposite conductivity type to the first region; wherein the junction is defined by a common surface shared by the first region and the second region, and wherein the gate electrode comprises polysilicon that is doped to have the same conductivity type as the first region.

15. The apparatus of claim 14 , wherein:

the gate electrode is undoped silicided polysilicon; and

the diode is a schottky diode.

16. The apparatus of claim 14 , wherein:

the thin gate insulator is less than 40 angstroms thick and comprises silicon dioxide;

the programming voltage is greater than 9 volts; and

the junction is at least 0.5 microns from the thin gate insulator.

17. The apparatus of claim 14 , wherein the gate electrode further comprises a region of undoped polysilicon; and

the region of undoped polysilicon is covered by a masking layer.