IP Library Granted Patent US 9,184,361
Granted Patent B2
US 9,184,361 · App. 14/293,713 · Granted Nov 10, 2015

Semiconductor light emitting device and method for manufacturing the same

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Quick Facts
Patent No.
US 9,184,361
App. No.
14/293,713
Granted
Nov 10, 2015
Kind
B2
Abstract

According to one embodiment, a semiconductor light emitting device includes: a semiconductor layer including a first face, a second face, a side face, and a light emitting layer; a p-side electrode provided on the second face; an n-side electrode provided on the side face; a first p-side metal layer provided on the p-side electrode; a first n-side metal layer provided on the periphery of the n-side electrode; a first insulating layer provided on a face on the second face side in the first n-side metal layer; a second p-side metal layer connected with the first p-side metal layer on the first p-side metal layer, and provided, extending from on the first p-side metal layer to on the first insulating layer; and a second n-side metal layer provided on a face on the second face side in the first n-side metal layer in a peripheral region of the semiconductor layer.

Claims (24)

1. A method for manufacturing a semiconductor light emitting device, comprising:

forming a first p-side metal layer connected electrically with a p-side electrode on the p-side electrode in a plurality of chips separated on a substrate, each of the plurality of chips including a semiconductor layer including a first face, a second face opposite to the first face, a side face and a light emitting layer, the p-side electrode provided on the second face and an n-side electrode provided on the side face;

transferring a target chip among the plurality of chips to a support;

forming a first n-side metal layer connected electrically with the n-side electrode on a periphery of the n-side electrode on the support;

removing the support and forming a first insulating layer on a surface of the first n-side metal layer from which the support has been removed;

forming a second p-side metal layer connected electrically with the first p-side metal layer on the first p-side metal layer and extending onto the first insulating layer in a first peripheral region of the semiconductor layer; and

forming a second n-side metal layer provided on the first n-side metal layer in a second peripheral region of the semiconductor layer and penetrating through the first insulating layer to be connected electrically with the first n-side metal layer, the second peripheral region being opposite the first peripheral region.

2. The method according to claim 1 , wherein:

a trench separating the plurality of semiconductor layers is also formed on a surface of the substrate, and a concave part and a convex part are formed on the surface of the substrate;

the side face of the semiconductor layer faces the trench;

a side face between the concave part and the convex part faces the trench;

the n-side electrode is formed on the side face of the semiconductor layer and on the side face between the concave part and the convex part;

the substrate is ground from a rear face side until reaching the trench to thereby separate the chip into a plurality of parts and the first p-side metal layer side is supported by the support;

the substrate remaining on the first face is removed to form a space surrounded by the n-side electrode on the first face; and

a phosphor layer is formed in the space.

3. The method according to claim 1 , wherein:

after the removal of the support, a surface of the first p-side metal layer is protruded from a surface of the first n-side metal layer to form a step between the surface of the first p-side metal layer and the surface of the first n-side metal layer;

the first insulating layer is formed on the surface of the first p-side metal layer and on the surface of the first n-side metal layer so as to cover the step; and

the first insulating layer on the surface of the first p-side metal layer is removed to expose the surface of the first p-side metal layer, while the first insulating layer is left on the surface of the first n-side metal layer.

4. The method according to claim 1 , wherein the target chip is supported by the support on the first p-side metal layer side before the transferring of the target chip.

5. The method according to claim 1 , further comprising removing the substrate from the target chip.

6. The method according to claim 1 , wherein

the first n-side metal layer has a first portion and a second portion,

the second p-side metal layer overlaps the first portion with the first insulating layer being interposed between the second p-side metal layer and the first portion, the second n-side metal layer is formed on the second portion.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2018
From: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 046986/0159 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2018
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 046364/0164 →