Method for fabricating semiconductor device

1. A method for fabricating semiconductor device, comprising:

providing a substrate having a transistor region and a resistor region;

forming a shallow trench isolation (STI) on the resistor region of the substrate;

forming a tank in the STI; and

forming a resistor in the tank and on two sides of the top surface of the STI outside the tank.

2. The method of claim 1 , wherein after forming the tank comprises:

forming an interfacial layer, a high-k dielectric layer, a barrier layer, and a polysilicon layer on the substrate;

performing an ion implantation process to implant a dopant into part of the polysilicon layer; and

patterning the interfacial layer, the high-k dielectric layer, the barrier layer, and the polysilicon layer to form a gate in the transistor region and a resistor in the resistor region.

3. The method of claim 2 , wherein the dopant comprise boron atoms.

4. The method of claim 2 , further comprising:

forming at least one spacer on the sidewalls of the gate and the resistor; and

forming a source/drain in the substrate adjacent to two sides of the spacer of the gate.

5. The method of claim 4 , further comprising:

forming a contact etch stop layer (CESL) to cover the gate and the resistor;

forming a first dielectric layer to cover the CESL;

performing a first planarizing process to partially remove the first dielectric layer and the CESL; and

performing an etching back process to expose the top of the gate, the surface of CESL on the polysilicon layer in the tank and the CESL on the polysilicon layer adjacent to two sides of the tank.

6. The method of claim 5 , further comprising:

performing a dry etching process to remove the polysilicon layer implanted with dopant in the transistor region and the resistor region;

performing a wet etching process to remove the polysilicon layer not implanted with dopant for forming a plurality of openings in the transistor region and the resistor region;

forming a work function metal layer and a conductive layer to fill the openings; and

performing a second planarizing process to partially remove the work function metal layer and the conductive layer such that the surface of the conductive layer being even with the surface of the first dielectric layer for forming a metal gate in the transistor region and a plurality of contacts adjacent to two sides of the tank in the resistor region.

7. The method of claim 6 , further comprising:

forming a passivation layer on the first dielectric layer;

forming a second dielectric layer on the passivation layer; and

forming a plurality of contact plugs in the passivation layer and the second dielectric layer for connecting the metal gate and the contacts.

8. The method of claim 7 , wherein the passivation layer comprises TiAlO or SiCN.