IP Library Granted Patent US 8,917,372
Granted Patent B2
US 8,917,372 · App. 14/295,627 · Granted Dec 23, 2014

Method of manufacturing a display device comprising first and second polarizing plate and phase difference plate combinations and a step of simultaneously polishing a second substrate and a semiconductor chip to have the same thickness as each other

Inventor: Masumitsu Ino (Kawagawa, JP)
Assignee: Japan Display West Inc.
H01J9/20
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Quick Facts
Patent No.
US 8,917,372
App. No.
14/295,627
Granted
Dec 23, 2014
Kind
B2
Abstract

A display device including: a first substrate with a pixel switch and drivers mounted thereon; a second substrate disposed in facing relation to the first substrate; a material layer held between the first substrate and the second substrate and having peripheral edges sealed by a seal member, the material layer having an electrooptical effect; and a semiconductor chip mounted as a COG component on the first substrate, the semiconductor chip having a control system configured to control the drivers; wherein the semiconductor chip having a thickness equal to the total thickness of the seal member and the second substrate or larger than the thickness of the seal member and smaller than the total thickness.

Claims (4)

1. A method of manufacturing a display device having a first substrate with a pixel switch and drivers mounted thereon, a second substrate disposed in facing relation to said first substrate, a material layer between said first substrate and said second substrate, a first polarizing plate and phase difference plate combination disposed between said first substrate and said material layer, a second polarizing plate and phase difference plate combination disposed between said second substrate and said material layer, and a seal member sealing said material layer, the method comprising:

a first step of mounting a semiconductor chip having a control system configured to control said drivers, as a COG component on said first substrate parallel to a region in which said seal member and said second substrate are stacked;

a second step of filling a space around said semiconductor chip with a protective fixing member thereby to secure said first substrate and said semiconductor chip to each other; and

a third step of simultaneously polishing said second substrate and said semiconductor chip to the same thickness as each other.

Priority Claims (1)
JP 2006-069539 · Mar 14, 2006 · national
Continuity (3)
Division 13588620 · Aug 17, 2012
Division 11684867 · Mar 12, 2007
Related Publication 20140287647A1 · Sep 25, 2014