Dividing a storage procedure

1. A method comprising:

adjusting one or more parameters for an erase operation for a set of non-volatile memory cells of a non-volatile memory element, by reducing a number of pulses for the erase operation from a default number of pulses such that the erase operation has a predetermined duration;

executing the adjusted erase operation for the set of memory cells for the predetermined duration; and

iteratively executing one or more additional adjusted, separate erase operations for the set of memory cells with predetermined durations until an erase verify voltage threshold is satisfied.

2. The method of claim 1 , further comprising executing a storage operation on the memory element between executing two of the adjusted erase operations.

3. The method of claim 1 , wherein the adjusted erase operation and the one or more additional adjusted erase operations comprise sub-operations of the same erase procedure for the set of non-volatile memory cells.

4. The method of claim 1 , wherein the adjusted erase operation and the one or more additional adjusted erase operations are executed without executing a suspend command for the non-volatile memory element.

5. The method of claim 1 , wherein the adjusted erase operation and the one or more additional adjusted erase operations are independently executable with separate erase commands.

6. The method of claim 1 , wherein a predefined duration for at least one of the adjusted erase operation and the one or more additional adjusted erase operations is shorter than a default time for an erase operation.

7. The method of claim 1 , wherein multiple erase operations of the adjusted erase operation and the one or more additional adjusted erase operations each comprise a ramp-up voltage increasing from a first voltage level to a second voltage level.

8. The method of claim 7 , further comprising increasing at least the first voltage for the ramp-up voltage for successively executed adjusted erase operations.

9. The method of claim 1 , further comprising increasing a number of erase pulses for successively executed erase operations of the adjusted erase operation and the one or more additional adjusted erase operations.

10. The method of claim 1 , further comprising increasing a start voltage for successively executed erase operations of the adjusted erase operation and the one or more additional adjusted erase operations.

11. An apparatus comprising:

a control module configured to adjust one or more parameters for an erase operation for a set of non-volatile memory cells of a non-volatile memory element such that the erase operation has a predetermined duration; and

an execution module configured to

execute the adjusted erase operation for the set of memory cells for the predetermined duration, and

iteratively execute one or more additional adjusted, separate erase operations for the set of memory cells with predetermined durations until an erase verify voltage threshold is satisfied, in response to a verify operation performed for each of the additional adjusted, separate erase operations, wherein multiple erase operations of the adjusted erase operation and the one or more additional adjusted erase operations each comprise a ramp-up voltage increasing from a first erase voltage level to a second erase voltage level.

12. The apparatus of claim 11 , further comprising a storage request module configured to execute a storage operation on the memory element between executing two of the adjusted erase operations.

13. The apparatus of claim 11 , further comprising an adjustment module configured to adjust one or more parameters for the adjusted erase operations from one or more default values for the erase operation.

14. The apparatus of claim 13 , wherein the one or more parameters comprise one or more of a loop count, a start erase voltage level, an erase voltage level step size, an erase verify voltage level, a maximum erase voltage, and an erase pulse duration.

15. The apparatus of claim 11 , wherein the adjusted erase operation and the one or more additional adjusted erase operations are executed without executing a suspend command for the non-volatile memory element.

16. A computer program product comprising a computer readable storage medium storing computer usable program code executable to perform operations, the operations comprising:

adjusting one or more parameters for an erase operation for a set of non-volatile memory cells of a non-volatile memory element, by reducing a number of pulses for the erase operation from a default number of pulses such that the erase operation has a predetermined duration;

executing the adjusted erase operation for the set of memory cells for the predetermined duration; and

iteratively executing one or more additional adjusted, separate erase operations for the set of memory cells with predetermined durations until an erase verify voltage threshold is satisfied, wherein multiple erase operations of the adjusted erase operation and the one or more additional adjusted erase operations each comprise a ramp-up voltage increasing from a first erase voltage level to a second erase voltage level;

executing a storage operation on the memory element between executing two of the adjusted erase operations.

17. The computer program product of claim 16 , the operations further comprising increasing a loop count for successively performed adjusted erase operations until an adjusted erase operation is verified as successful.

18. The computer program product of claim 16 , the operations further comprising increasing a start voltage for successively performed adjusted erase operations until an adjusted erase operation is verified as successful.