Nanowire LED structure with decreased leakage and method of making same

1. A semiconductor device, comprising:

a plurality of first conductivity type semiconductor nanowire cores located over a support;

an insulating mask layer located over the support, wherein the nanowire cores comprise semiconductor nanowires epitaxially extending from portions of a semiconductor surface of the support exposed through openings in the insulating mask layer;

a plurality of second conductivity type semiconductor shells extending over and around the respective nanowire cores;

a first electrode layer that contacts the second conductivity type semiconductor shells and extends into spaces between the semiconductor shells;

an insulating layer located between the insulating mask layer and the first electrode layer in the spaces between the semiconductor shells; and

an active region shell around each of the plurality of semiconductor nanowire cores;

wherein the device comprises a light emitting diode (LED) device; and

wherein the active region shell comprises at least one quantum well and each of the plurality of the second conductivity type semiconductor shells surrounds the at least one quantum well to form a light emitting p-i-n junction at each semiconductor nanowire core surrounded by the at least one quantum well.

2. The device of claim 1 , wherein:

each of the semiconductor shells comprises a semiconductor foot portion which extends on the insulating masking layer in the spaces between the semiconductor shells; and

the insulating layer is located on the semiconductor foot portion such that the first electrode layer contacts the insulating layer and does not contact the semiconductor foot portion.

3. The device of claim 2 , wherein:

each of the plurality of the second conductivity type semiconductor shells comprises a p-AlGaN inner shell and p-GaN outer shell;

the semiconductor foot portion comprises a p-AlGaN foot portion of the p-AlGaN inner shell; and

the p-AlGaN foot portion connects to the p-AlGaN inner shell under the p-GaN outer shell.

4. The device of claim 1 , further comprising a first conductivity type AlGaN shell, wherein:

the first conductivity type AlGaN shell is located between the active region shell and a respective one of the plurality of first conductivity semiconductor nanowire cores;

the first conductivity type AlGaN shell comprises a first conductivity type AlGaN foot portion which extends on the insulating masking layer in the spaces between the second conductivity type semiconductor shells;

the insulating layer is located on the first conductivity type AlGaN foot portion such that the first electrode layer contacts the insulating layer and does not contact the first conductivity type AlGaN foot portion;

each of the plurality of the second conductivity type semiconductor shells comprises a second conductivity type GaN outer shell; and

the first conductivity type AlGaN foot portion connects to the first conductivity type AlGaN shell under the second conductivity type GaN outer shell and under the active region shell.

5. The device of claim 4 , wherein the first conductivity type comprises n-type, the second conductivity type comprises p-type and the first electrode layer comprises a p-electrode layer.

6. The device of claim 5 , further comprising a second electrode layer which electrically connects to the n-type semiconductor nanowire cores.

7. The device of claim 6 , wherein the support comprises an n-type semiconductor buffer layer on a substrate.

8. The device of claim 7 , wherein the buffer layer comprises an n-GaN or n-AlGaN layer, the semiconductor nanowire cores comprise n-GaN nanowires, the at least one quantum well comprises an InGaN/GaN quantum well and the first electrode layer comprises a transparent conductive oxide (TCO).

9. The device of claim 1 , wherein the insulating layer comprises a spin-on dielectric.

10. The device of claim 9 , wherein the spin-on dielectric comprises a spin-on glass layer having a curved upper surface.

11. A method of making a semiconductor device, comprising:

epitaxially growing a plurality of first conductivity type semiconductor nanowire cores from portions of a semiconductor surface of a support exposed through openings in an insulating mask layer on the support;

forming a plurality of second conductivity type semiconductor shells extending over and around the respective nanowire cores;

forming an insulating layer over the insulating mask layer in spaces between the semiconductor shells, such that tips and at least upper portions of sidewalls of the semiconductor shells are exposed in the insulating layer; and

forming a first electrode layer, wherein the first electrode layer contacts the exposed tips and the at least upper portions of sidewalls of semiconductor shells and the first electrode layer contacts the insulating layer in the spaces between the semiconductor shells;

wherein the step of forming the insulating layer comprises spin-coating a spin-on dielectric layer;

wherein the spin-on dielectric layer thickness is greater over the insulating mask layer in the spaces between the semiconductor shells than on the sidewalls of the semiconductor shells; and

further comprising isotropically, partially etching the spin-on dielectric layer to remove the spin-on dielectric from the at least upper portions of the semiconductor shell sidewalls and expose the at least upper portions of the semiconductor shell sidewalls while the spin-on dielectric layer remains in the spaces between the semiconductor shells.

12. The method of claim 11 , wherein:

the step of forming the plurality of second conductivity type semiconductor shells comprises forming substantially single crystal semiconductor shell portions extending over and around the respective semiconductor nanowire cores and polycrystalline semiconductor foot portions which extend on the insulating masking layer in the spaces between the semiconductor shells; and

the step of forming the first electrode layer comprises forming a continuous first electrode layer on the exposed tips and the at least upper portions of the sidewalls of the semiconductor shells and on the insulating layer in the spaces between the semiconductor shells such that the first electrode layer does not contact the polycrystalline semiconductor foot portions.

13. The method of claim 12 , wherein:

the step of forming the plurality of second conductivity type semiconductor shells each comprise forming inner p-AlGaN inner shells at a temperature below 850° C. and forming p-GaN outer shells;

the polycrystalline semiconductor foot portions comprise a polycrystalline p-AlGaN foot portion of the p-AlGaN inner shells; and

the p-GaN outer shells are formed over the p-AlGaN inner shells and the p-AlGaN foot portions such that the p-AlGaN foot portions connect to the respective p-AlGaN inner shells under the respective p-GaN outer shells.

14. The method of claim 11 , further comprising forming first conductivity type AlGaN shells at a temperature below 850° C. between respective active region shells and the semiconductor nanowire cores, wherein:

the step of forming the first conductivity type AlGaN shells comprises forming substantially single crystal AlGaN shell portions extending over and around the respective semiconductor nanowire cores and first conductivity type polycrystalline AlGaN foot portions which extend on the insulating masking layer in the spaces between the second conductivity type semiconductor shells; and

the step of forming the first electrode layer comprises forming a continuous first electrode layer on the exposed tips and the at least upper portions of the sidewalls of the second conductivity type semiconductor shells and on the insulating layer in the spaces between the second conductivity type semiconductor shells such that the first electrode layer does not contact the polycrystalline AlGaN foot portions; and

the first conductivity type polycrystalline AlGaN foot portions connect to the respective first conductivity type AlGaN shells under the respective second conductivity type semiconductor shells and under the respective active region shells.

15. The method of claim 11 , wherein the insulating layer comprises a spin-on glass layer having a curved upper surface.

16. The method of claim 15 , further comprising forming an active region shell around each of the plurality of first conductivity type semiconductor nanowire cores, wherein the device comprises a light emitting diode (LED) device.

17. The method of claim 16 , wherein the first conductivity type comprises n-type, the second conductivity type comprises p-type and the first electrode layer comprises a p-electrode layer.

18. The method of claim 17 , further comprising a second electrode layer which electrically connects to the n-type semiconductor nanowire cores.

19. The method of claim 18 , wherein the support comprises an n-type semiconductor buffer layer on a substrate, the buffer layer comprises an n-GaN or n-AlGaN layer, the semiconductor nanowire cores comprise n-GaN nanowires, the at least active region shell comprises an InGaN/GaN quantum well and the first electrode layer comprises a transparent conductive oxide (TCO).