Low-G MEMS acceleration switch
A motion-sensitive low-G MEMS acceleration switch, which is a MEMS switch that closes at low-g acceleration (e.g., sensitive to no more than 10 Gs), is proposed. Specifically, the low-G MEMS acceleration switch has a base, a sensor wafer with one or more proofmasses, an open circuit that includes two fixed electrodes, and a contact plate. During acceleration, one or more of the proofmasses move towards the base and connects the two fixed electrodes together, resulting in a closing of the circuit that detects the acceleration. Sensitivity to low-G acceleration is achieved by proper dimensioning of the proofmasses and one or more springs used to support the proofmasses in the switch.
1. A MEMS acceleration switch comprising:
a base;
a first electrode coupled to the base;
a second electrode coupled to the base and spaced apart from the first electrode;
an SOI wafer comprising:
a proofmass comprising multiple layers of the SOI wafer and formed by etching into the SOI wafer around the proofmass down to a device layer, wherein the proofmass is coupled to the SOI wafer only by portions of the device layer surrounding the proofmass; and,
a contact plate coupled to the SOI wafer adjacent the proofmass;
wherein the base is coupled to and spaced apart from the SOI wafer such that the contact plate forms a gap with the first and second electrodes and the proofmass is designed to translate with respect to the SOI wafer such that the contact plate closes the gap under an acceleration and electrically connects the first and second electrodes.
2. The MEMS acceleration switch of claim 1 , wherein the switch is a flip chip.
3. The MEMS acceleration switch of claim 2 , further comprising a plurality of vias that provide electrical communication from the first and second electrodes through the base to an opposite side of the base from the first and second electrodes.
4. The MEMS acceleration switch of claim 1 , further comprising a lid coupled to the SOI wafer.
5. The MEMS acceleration switch of claim 1 , wherein the portions of the device layer surrounding the proofmass are substantially thinner than the proofmass.
6. The MEMS acceleration switch of claim 1 , wherein the portions of the device layer surrounding the proofmass are springs.
7. The MEMS acceleration switch of claim 1 , wherein the portions of the device layer surrounding the proofmass have a thickness defined by the device layer.
8. The MEMS acceleration switch of claim 1 , wherein the portions of the device layer surrounding the proofmass form discrete connections to the surrounding SOI wafer and other portions of the device layer surrounding the proofmass have been completely removed to form the discrete connections.
9. A method of making a MEMS acceleration switch comprising:
forming a base;
coupling a first electrode to the base;
coupling a second electrode to the base spaced apart from the first electrode;
coupling a SOI wafer to the base;
forming a proofmass from multiple layers of the SOI wafer by etching into the SOI wafer around the proofmass down to a device layer such that the proofmass is coupled to the surrounding SOI wafer only by portions of the device layer surrounding the proofmass; and,
coupling a contact plate to the SOI wafer adjacent the proofmass;
wherein the base is spaced apart from the SOI wafer such that the contact plate forms a gap with the first and second electrodes and the proofmass is designed to translate with respect to the surrounding SOI wafer such that the contact plate closes the gap under an acceleration and electrically connects the first and second electrodes.
10. The method of claim 9 , wherein the switch is formed in a flip chip design.
11. The method of claim 9 , further comprising forming a plurality of vias that provide electrical communication from the first and second electrodes through the base to an opposite side of the base from the first and second electrodes.
12. The method of claim 9 , further comprising coupling a lid to the SOI wafer.
13. The method of claim 9 , wherein the portions of the device layer surrounding the proofmass are substantially thinner than the proofmass.
14. The method of claim 9 , wherein the portions of the device layer surrounding the proofmass are springs.
15. The method of claim 9 , wherein the portions of the device layer surrounding the proofmass have a thickness defined by the device layer.
16. The method of claim 9 , wherein the portions of the device layer surrounding the proofmass form discrete connections to the surrounding SOI wafer and other portions of the device layer surrounding the proofmass have been completely removed to form the discrete connections.