IP Library Granted Patent US 9,164,848
Granted Patent B2
US 9,164,848 · App. 14/300,121 · Granted Oct 20, 2015

Variable partitioning in a hybrid memory subsystem

Inventor: Ronald H Sartore (Poway, CA)
Assignee: AgigA Tech Inc
G06F11/1458G06F1/30G06F1/305G06F12/023G06F12/0638G06F12/0868G11C7/10G11C11/005G06F12/0871Y02B60/1225
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Quick Facts
Patent No.
US 9,164,848
App. No.
14/300,121
Granted
Oct 20, 2015
Kind
B2
Abstract

A memory module includes a volatile memory, a non-volatile memory, and a memory controller adapted to present to a host system external to the memory module an address space that includes an address space of the volatile memory and excludes all addresses of the non-volatile memory capacity. The module includes logic to copy the contents of the volatile memory to memory locations of the nonvolatile memory capacity reserved for backup of the volatile memory, using power from a backup power interface, when suitable power from the host system is unavailable, wherein the memory controller reserves for backup of the volatile memory an amount of nonvolatile memory storage capacity that is at least twice a memory storage capacity of the volatile memory.

Claims (20)

1. A memory module comprising:

a volatile memory;

a non-volatile memory;

a memory controller adapted to present to a host system external to the memory module an address space that includes an address space of the volatile memory and excludes all addresses of a non-volatile memory capacity;

a primary power supply input adapted to receive power from the host system;

a backup power interface; and

logic to copy contents of the volatile memory to memory locations of the non-volatile memory capacity reserved for backup of the volatile memory, using power from the backup power interface, when suitable power from the host system is unavailable, wherein the memory controller reserves for backup of the volatile memory an amount of the non-volatile memory capacity that is at least twice a memory storage capacity of the volatile memory.

2. The memory module of claim 1 , further comprising:

the address space presented to the host system including only addresses in the volatile memory and no addresses in the memory controller or the non-volatile memory.

3. A data processing device, comprising:

a host system including a volatile memory interface to a plug-in memory module;

the plug-in memory module comprising:

a volatile memory;

a non-volatile memory;

a memory controller adapted to present to the host system an address space that includes an address space of the volatile memory and excludes all addresses of the non-volatile memory;

a primary power supply input adapted to receive power from the host system;

a backup power interface; and

logic to copy the contents of the volatile memory to memory locations of the non-volatile memory capacity reserved for backup of the volatile memory, using power from the backup power interface, when suitable power from the host system is unavailable, wherein the memory controller reserves for backup of the volatile memory an amount of the non-volatile memory capacity that is at least twice a memory storage capacity of the volatile memory.

4. The memory module of claim 1 , further comprising:

the address space presented to the host system including only addresses in the volatile memory and no addresses in the memory controller or the non-volatile memory.

Assignments (2)
MERGER Recorded Apr 23, 2025
From: AGIGA TECH, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 070926/0472 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2017
From: SARTORE, RONALD H.
To: AGIGA TECH INC.
Reel/Frame 043918/0581 →
Continuity (4)
Continuation 13481896 · May 28, 2012
Continuation 13287898 · Nov 2, 2011
Continuation 11881346 · Jul 25, 2007
Related Publication 20140359237A1 · Dec 4, 2014