Electric field gap device and manufacturing method
View Patent ↗The invention provides a method of forming an electric field gap device, such as a lateral field emission ESD protection structure, in which a cathode layer is formed between dielectric layers. Anode channels are formed and they are lined with a sacrificial dielectric layer. Conductive anode pillars are formed in the anode channels, and then the sacrificial dielectric layer is etched away in the vicinity of the anode pillars. The etching leaves a suspended portion of the cathode layer which defines a lateral gap to an adjacent anode pillar. This portion has a sharp end face defined by the corners of the cathode layer and the lateral gap can be defined accurately as it corresponds to the thickness of the sacrificial dielectric layer.
1. A method of forming an electric field gap structure, comprising:
forming a first dielectric ( 12 ) layer over a substrate ( 10 );
forming a cathode layer ( 20 ) over the first dielectric layer ( 12 );
forming a second dielectric layer ( 22 ) over the cathode layer ( 20 );
etching anode channels through the second dielectric layer ( 22 ) and the cathode layer ( 20 ) and into the first dielectric layer ( 12 );
lining the resulting surface with a third dielectric layer ( 24 );
forming conductive anode pillars ( 27 ) in the anode channels;
etching away the third dielectric layer ( 24 ) and the second dielectric layer ( 22 ) in the vicinity of the anode pillars ( 17 ), and at least partially etching away the first dielectric layer ( 12 ) in the vicinity of the anode pillars ( 17 ), thereby to leave a suspended portion ( 34 ) of the cathode layer ( 20 ) which defines a lateral gap to an adjacent anode pillar ( 17 ).
2. A method as claimed in claim 1 , further comprising forming connection pillars ( 18 ) through the first dielectric layer ( 12 ) to the substrate ( 10 ), and wherein the cathode layer ( 20 ) is formed over the first dielectric layer ( 12 ) and the connection pillars ( 18 ).
3. A method as claimed in claim 2 , wherein the lateral field emission ESD protection structure is formed over an integrated circuit, and wherein the connection pillars ( 18 ) connect to a metal layer within the integrated circuit.
4. A method as claimed in any preceding claim, further comprising forming a packaging layer ( 32 ) over the anode pillars.
5. A method as claimed in any preceding claim, wherein the first, second and third dielectric layers ( 12 , 22 , 24 ) each comprise silicon dioxide or silicon nitride and wherein the first, second and third dielectric layers are preferably formed of the same material.
6. A method as claimed in any preceding claim, wherein the connection pillars ( 18 ) comprise a stack of one or more of titanium, titanium nitride and tungsten.
7. A method as claimed in any preceding claim, wherein the anode channels extend only partially into the first dielectric layer ( 12 ).
8. A method as claimed in any preceding claim, wherein the thickness of third dielectric layer ( 24 ) is selected to correspond to the desired anode-cathode gap.
9. A method as claimed in any preceding claim, wherein the material of the anode pillars ( 17 ) is also used to form an anode contact ( 28 ) over the third dielectric layer outside the region where the anode pillars ( 17 ) are formed.
10. An electric field gap structure, comprising:
a first dielectric layer ( 12 ) over a substrate ( 10 );
a cathode layer ( 20 ) over the first dielectric layer ( 12 ) which defines cathode portions which have an edge region with a portion of the first dielectric layer ( 12 ) beneath under-etched away thereby to define laterally projecting edge regions ( 34 );
conductive anode pillars ( 17 ) which extend into the first dielectric layer ( 12 ), wherein a lateral spacing is defined between each laterally projecting edge region and an adjacent anode pillar ( 17 );
a second dielectric layer ( 22 ) over the cathode layer ( 20 ), wherein the second dielectric layer is absent over the edge regions ( 34 ); and
a third dielectric layer ( 24 ) over the second dielectric layer ( 22 ), wherein the thickness of the third dielectric layer ( 24 ) corresponds to the lateral spacing.
11. A structure as claimed in claim 10 , further comprising a packaging layer ( 32 ) over the anode pillars.
12. A structure as claimed in claim 10 or 11 , wherein the first, second and third dielectric layers ( 12 , 22 , 24 ) each comprise silicon dioxide or silicon nitride.
13. A structure as claimed in claim 10 , 11 or 12 , wherein the anode channels extend only partially into the first dielectric layer ( 12 ).
14. A structure as claimed in any one of claims 10 to 13 , comprising an anode contact ( 28 ) over the third dielectric layer ( 24 ) outside the region where the anode pillars are formed and formed from the same material as the anode pillars.
15. A structure as claimed in one of claims 10 to 14 , formed over an integrated circuit, further comprising connection pillars which extend from the cathode layer ( 20 ) through the first dielectric layer to a metal layer within the integrated circuit.