Circuits and techniques for detecting an open pin condition of an integrated circuit
An integrated circuit an open pin detector includes a current source coupled to the pin, a comparator having a first input coupled to the pin, a second input responsive to a threshold voltage, and an output at which a comparator output signal is provided. A controller is responsive to the comparator output signal to provide an enable signal to the current source and an open pin signal indicative of an open pin condition at the pin. A method for detecting an open pin condition of a pin of an integrated circuit includes comparing the pin voltage to a first threshold voltage level, initiating open pin detection in response to the pin voltage falling below the first threshold voltage level, such as by providing a current to the pin, and indicating an open pin condition if the pin voltage rises to exceed a second threshold voltage level within a predetermined time interval. Also described is preventing the pin voltage from exceeding a predetermined voltage level during open pin detection.
1. An integrated circuit, comprising:
a current source coupled to a pin of the integrated circuit;
a comparator having a first input coupled to the pin, a second input selectively coupled to a first threshold voltage or to a second threshold voltage, and an output at which a comparator output signal is provided; and
a controller responsive to the comparator output signal, the controller having an output coupled to the current source to provide an enable signal to the current source and the controller configured to provide an open pin signal indicative of an open condition at the pin, wherein when the enable signal is at a first level, the first threshold voltage is coupled to the first comparator input and the current source is enabled, and when the enable signal is at a second level, the second threshold voltage is coupled to the first comparator input and the current source is disabled.
2. The integrated circuit of claim 1 further comprising a clamp coupled to the pin to prevent a voltage at the pin from exceeding a predetermined level.
3. The integrated circuit of claim 1 further comprising a current sink coupled to the pin.
4. The integrated circuit of claim 1 wherein the integrated circuit is a regulator control circuit comprising a switch and wherein the switch is turned off in response to the open pin signal.
5. The integrated circuit of claim 4 wherein a regulated output voltage of the regulator is coupled to the pin.
6. The integrated circuit of claim 1 wherein the controller comprises a state machine.
7. The integrated circuit of claim 2 wherein the clamp comprises a resistor coupled between the pin and a reference voltage.
8. A method for detecting an open pin condition of a pin of an integrated circuit, comprising:
comparing, by a comparator, a voltage at the pin to a first threshold voltage;
in response to the voltage at the pin falling below the first threshold voltage, initiating an open pin detection by sourcing a current to the pin and comparing, by the comparator, the voltage at the pin to a second threshold voltage; and
indicating an open pin condition if the voltage at the pin rises to exceed the second threshold voltage within a predetermined time interval.
9. The method of claim 8 further comprising preventing the voltage at the pin from exceeding a predetermined level.
10. The method of claim 8 further comprising re-initiating the open pin detection after an open pin condition is indicated.
11. The method of claim 9 wherein the integrated circuit is a regulator control circuit and the predetermined level is selected according to a VOUT bias enable threshold.
12. The method of claim 8 wherein initiating the open pin detection further comprises changing the threshold voltage at a comparator input from the first threshold voltage to the second threshold voltage.
13. The method of claim 8 wherein the predetermined time interval is a predetermined number of clock cycles.
14. The method of claim 13 wherein the integrated circuit is a switching regulator control circuit and the clock cycles are switching clock cycles.
15. The method of claim 14 wherein a regulated output voltage of the switching regulator is coupled to the pin.
16. The method of claim 8 further comprising sinking a current from the pin.
17. A method for detecting an open pin condition of a pin of an integrated circuit, comprising:
providing a current to the pin, in response to a voltage at the pin falling below a first threshold voltage;
determining, by a comparator, if the voltage at the pin rises to exceed a second threshold within a predetermined time interval; and
preventing the pin voltage from exceeding a predetermined voltage level.
18. The method of claim 17 wherein determining if the voltage at the pin changes by a predetermined amount comprises comparing, by the comparator, the voltage at the pin to the first threshold level at a beginning of the predetermined time interval and to the second threshold level at an end of the predetermined time interval.
19. The method of claim 17 wherein the integrated circuit is a switching regulator control circuit and wherein the predetermined voltage level is selected according to a VOUT bias enable threshold.