Bank-level fault management in a memory system
According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including a plurality of memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition.
1. A memory system, comprising:
a plurality of ranks, each rank comprising a plurality of memory devices each having a plurality of banks; and
a memory buffer device coupled to at least one of the ranks, the memory system configured to:
detect a first error in a first bank number of a first memory device of a rank;
mark the first bank number of the first memory device with a bank-level chip mark, the bank-level chip mark isolating declaration of an error condition to the first bank number;
detect a second error in the first bank number of a second memory device of the rank;
based on a determination that a non-faulty bank is available at a second bank number, overwrite in-use data storage of the second bank number with data associated with the first bank number of the second memory device and steer access requests for the first bank number of the second memory device to the non-faulty bank having the second bank number; and
perform a bank-level fault management action based on the bank-level chip mark to accommodate the error condition by accessing the second bank number to accommodate the second error and correcting the first error using an error-correcting code decoder in combination with accessing the first bank number and the second bank number.
2. The memory system of claim 1 , wherein the memory system is further configured to:
receive an access request for the second bank number; and
use the error-correcting code decoder to generate recovery data associated with the in-use data storage of the non-faulty bank having the second bank number after being overwritten by the data associated with the first bank number of the second memory device.
3. The memory system of claim 1 , wherein the non-faulty bank having the second bank number is located in the second memory device.
4. The memory system of claim 1 , wherein the non-faulty bank is located on a second rank.
5. The memory system of claim 4 , wherein the rank and the second rank are located on separate memory modules coupled to the memory buffer device that controls bank steering between the rank and the second rank.
6. The memory system of claim 1 , wherein the memory system is further configured to:
mark the first bank number as a faulty bank based on detecting a subsequent error condition at the first bank number comprising the bank-level chip mark; and
support address range de-allocation for an address space of the faulty bank.