Group III-N transistors on nanoscale template structures
A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.
1. A mobile computing device, comprising:
a touchscreen;
a battery;
an antenna;
a DC-to-DC converter coupled to the battery; and
a wireless transmitter further including a power amplifier (PA), wherein at least one of the DC-to-DC converter and the PA comprises a III-N field effect transistor (FET) disposed on a silicon substrate, the FET comprising:
an anchor disposed over the substrate;
a first and second group III-N device layer stack physically separated from each other by the anchor, and each stack with a c-axis extending in opposite directions from the anchor and substantially parallel to a surface plane of the substrate; and
a gate stack disposed over the III-N device layer stacks to control a conductivity of a channel semiconductor layer in each of the III-N device layer stacks, wherein the channel semiconductor layer has a conduction band offset from the anchor material.
2. The mobile computing device of claim 1 where the DC-to-DC converter comprises a first III-N FET as in claim 1 , and the PA employs a second III-N FET as in claim 1 .
3. The mobile computing device of claim 1 , wherein the anchor further comprises a silicon fin having sidewalls with a (111) or (110) surface, the sidewalls substantially perpendicular to the III-N device layer stack c-axis.
4. The mobile computing device of claim 3 , wherein the channel semiconductor layer comprises InGaN with 20% In, or less.
5. The mobile computing device of claim 3 , wherein the silicon fin has a top surface minimum dimension of no more than 20 nm and wherein the sidewalls have a z-height no greater than 100 nm.
6. The mobile computing device of claim 1 , wherein the anchor further comprises a silicon-based dielectric fin.
7. The mobile computing device of claim 6 , wherein the anchor further comprises silicon dioxide in contact with a first crystalline transition layer disposed between the silicon dioxide and a first of the semiconductor channel layers, the silicon dioxide in further contact with a second crystalline transition layer disposed between the silicon dioxide and a second of the semiconductor channel layers.
8. The mobile computing device of claim 1 , wherein the anchor further comprises a gate dielectric layer, and wherein the gate dielectric layer is further disposed over a III-N polarization layer of each of the III-N device layer stacks.
9. The mobile computing device of claim 8 , wherein the anchor further comprises a gate electrode material, and wherein the gate dielectric layer is disposed between the gate electrode material and each of the first and second III-N device layer stacks.
10. The mobile computing device of claim 1 , wherein each of the III-N device layer stacks further comprises:
a channel semiconductor layer of GaN disposed on a transition layer; and
a polarization layer of AlN, AlInN, AlGaN, or AlInGaN disposed on the GaN channel semiconductor layer.
11. The mobile computing device of claim 10 , wherein the transition layer further comprises at least one of: a crystalline oxide, AlN, AlInN, or AlGaN.